MT29C4G48MAZAPAKD-5 E IT Micron, MT29C4G48MAZAPAKD-5 E IT Datasheet - Page 10

• Manufacturer Part Number: MT29C4G48MAZAPAKD-5 E IT
• Manufacturer: Micron

Figure 102: Functional Block Diagram (x16) .................................................................................................. 136
Figure 103: Functional Block Diagram (x32) .................................................................................................. 137
Figure 104: Typical Self Refresh Current vs. Temperature ............................................................................... 146
Figure 105: ACTIVE Command ..................................................................................................................... 158
Figure 106: READ Command ........................................................................................................................ 159
Figure 107: WRITE Command ...................................................................................................................... 160
Figure 108: PRECHARGE Command ............................................................................................................. 161
Figure 109: DEEP POWER-DOWN Command ................................................................................................ 162
Figure 110: Simplified State Diagram ............................................................................................................ 168
Figure 111: Initialize and Load Mode Registers .............................................................................................. 170
Figure 112: Alternate Initialization with CKE LOW ......................................................................................... 171
Figure 113: Standard Mode Register Definition ............................................................................................. 172
Figure 114: CAS Latency ............................................................................................................................... 175
Figure 115: Extended Mode Register ............................................................................................................. 176
Figure 116: Status Read Register Timing ........................................................................................................ 178
Figure 117: Status Register Definition ........................................................................................................... 179
Figure 118: READ Burst ................................................................................................................................ 182
Figure 119: Consecutive READ Bursts ........................................................................................................... 183
Figure 120: Nonconsecutive READ Bursts ..................................................................................................... 184
Figure 121: Random Read Accesses ............................................................................................................... 185
Figure 122: Terminating a READ Burst .......................................................................................................... 186
Figure 123: READ-to-WRITE ......................................................................................................................... 187
Figure 124: READ-to-PRECHARGE ................................................................................................................ 188
Figure 125: Data Output Timing –
Figure 126: Data Output Timing –
Figure 127: Data Output Timing –
Figure 128: Data Input Timing ...................................................................................................................... 193
Figure 129: Write – DM Operation ................................................................................................................. 194
Figure 130: WRITE Burst ............................................................................................................................... 195
Figure 131: Consecutive WRITE-to-WRITE .................................................................................................... 196
Figure 132: Nonconsecutive WRITE-to-WRITE .............................................................................................. 196
Figure 133: Random WRITE Cycles ............................................................................................................... 197
Figure 134: WRITE-to-READ – Uninterrupting .............................................................................................. 198
Figure 135: WRITE-to-READ – Interrupting ................................................................................................... 199
Figure 136: WRITE-to-READ – Odd Number of Data, Interrupting .................................................................. 200
Figure 137: WRITE-to-PRECHARGE – Uninterrupting .................................................................................... 201
Figure 138: WRITE-to-PRECHARGE – Interrupting ........................................................................................ 202
Figure 139: WRITE-to-PRECHARGE – Odd Number of Data, Interrupting ....................................................... 203
Figure 140: Bank Read – With Auto Precharge ................................................................................................ 206
Figure 141: Bank Read – Without Auto Precharge .......................................................................................... 207
Figure 142: Bank Write – With Auto Precharge ............................................................................................... 208
Figure 143: Bank Write – Without Auto Precharge .......................................................................................... 209
Figure 144: Auto Refresh Mode ..................................................................................................................... 210
Figure 145: Self Refresh Mode ....................................................................................................................... 212
Figure 146: Power-Down Entry (in Active or Precharge Mode) ....................................................................... 213
Figure 147: Power-Down Mode (Active or Precharge) .................................................................................... 214
Figure 148: Deep Power-Down Mode ............................................................................................................ 215
Figure 149: Clock Stop Mode ........................................................................................................................ 216
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
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168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
QH, and Data Valid Window (x16) ................................................. 189
QH, and Data Valid Window (x32) ................................................. 190
DQSCK ....................................................................................... 191
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