MT29C4G48MAZAPAKD-5 E IT Micron, MT29C4G48MAZAPAKD-5 E IT Datasheet - Page 68

• Manufacturer Part Number: MT29C4G48MAZAPAKD-5 E IT
• Manufacturer: Micron

Figure 39: READ PAGE (00h-30h) Operation
Figure 40: READ PAGE (00h-30h) Operation with Internal ECC Enabled
READ PAGE CACHE SEQUENTIAL (31h)
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
Cycle type
I/O[7:0]
I/O[7:0]
RDY
RDY
Command
00h
00h
Address
Address
C1
output begins at the column address last specified in the READ PAGE (00h-30h) com-
mand. The RANDOM DATA READ TWO-PLANE (06h-E0h) command is used to enable
data output in the other cache registers.
The READ PAGE CACHE SEQUENTIAL (31h) command reads the next sequential page
within a block into the data register while the previous page is output from the cache
register. This command is accepted by the die (LUN) when it is ready
(RDY = 1, ARDY = 1). It is also accepted by the die (LUN) during READ PAGE CACHE
(31h, 00h-31h) operations (RDY = 1 and ARDY = 0).
To issue this command, write 31h to the command register. After this command is is-
sued, R/B# goes LOW and the die (LUN) is busy (RDY = 0, ARDY = 0) for
t
(RDY = 1, ARDY = 0), indicating that the cache register is available and that the specified
page is copying from the NAND Flash array to the data register. At this point, data can
be output from the cache register beginning at column address 0. The RANDOM DATA
READ (05h-E0h) command can be used to change the column address of the data being
output from the cache register.
The READ PAGE CACHE SEQUENTIAL (31h) command can be used to cross block boun-
daries. If the READ PAGE CACHE SEQUENTIAL (31h) command is issued after the last
page of a block is read into the data register, the next page read will be the next logical
block in which the 31h command was issued. Do not issue the READ PAGE CACHE SE-
QUENTIAL (31h) to cross die (LUN) boundaries. Instead, issue the READ PAGE CACHE
LAST (3Fh) command.
RCBSY, R/B# goes HIGH and the die (LUN) is busy with a cache operation
Address
Address
C2
Address
Address
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
R1
Address
Address
Address
R2
68
Address
30h
R3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Command
30h
t WB
70h
t R_ECC
SR bit 0 = 0 READ successful
SR bit 1 = 0 READ error
Status
t R
00h
t RR
© 2009 Micron Technology, Inc. All rights reserved.
D
D n
OUT
Read Operations
D
OUT
D
D n+1
(serial access)
OUT
t
RCBSY. After
D
D n+2
OUT