MT29C4G48MAZAPAKD-5 E IT Micron, MT29C4G48MAZAPAKD-5 E IT Datasheet - Page 104

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MT29C4G48MAZAPAKD-5 E IT

Manufacturer Part Number
MT29C4G48MAZAPAKD-5 E IT
Description
Manufacturer
Micron
Datasheet
Figure 75: TWO-PLANE PROGRAM PAGE CACHE MODE
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
R/B#
R/B#
R/B#
I/Ox
I/Ox
I/Ox
1
2
80h
80h
80h
Address/data input
Address/data input
Address/data input
1st plane
1st plane
1st plane
11h
11h
11h
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
t
t
t
DBSY
DBSY
DBSY
104
80h
80h
80h
Address/data input
Address/data input
Address/data input
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2nd plane
2nd plane
2nd plane
15h
15h
10h
Two-Plane Operations
© 2009 Micron Technology, Inc. All rights reserved.
t
LPROG
t
t
CBSY
CBSY
1
2

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