MT29C4G48MAZAPAKD-5 E IT Micron, MT29C4G48MAZAPAKD-5 E IT Datasheet - Page 167

• Manufacturer Part Number: MT29C4G48MAZAPAKD-5 E IT
• Manufacturer: Micron

Table 54: Truth Table – CKE
Notes 1–4 apply to all parameters in this table
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
Current State
Active power-down
Deep power-down
Precharge power-down
Self refresh
Active power-down
Deep power-down
Precharge power-down
Self refresh
Bank(s) active
All banks idle
All banks idle
All banks idle
Notes:
CKE
1. CKE
2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.
3. COMMAND
4. All states and sequences not shown are illegal or reserved.
5. DESELECT or NOP commands should be issued on each clock edge occurring during the
6. After exiting deep power-down mode, a full DRAM initialization sequence is required.
7. The clock must toggle at least two times during the
H
H
H
H
H
H
L
L
L
L
L
L
L
L
n - 1
ous clock edge.
MAND
t
XP or
n
CKE
is the logic state of CKE at clock edge n; CKE
H
H
H
H
H
H
L
L
L
L
L
L
L
L
t
n
XSR period.
.
n
n
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
is the command registered at clock edge n, and ACTION
See Table 53 (page 165)
See Table 53 (page 165)
BURST TERMINATE
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
AUTO REFRESH
COMMAND
167
X
X
X
X
n
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Maintain precharge power-down
Precharge power-down entry
Maintain active power-down
Maintain deep power-down
Exit precharge power-down
Active power-down entry
Deep power-down entry
Exit active power-down
Exit deep power-down
n - 1
Maintain self refresh
Self refresh entry
t
Exit self refresh
XSR period.
was the state of CKE at the previ-
ACTION
© 2009 Micron Technology, Inc. All rights reserved.
n
n
is a result of COM-
Truth Tables
Notes
5, 7
5
6