MT29C4G48MAZAPAKD-5 E IT Micron, MT29C4G48MAZAPAKD-5 E IT Datasheet - Page 25

• Manufacturer Part Number: MT29C4G48MAZAPAKD-5 E IT
• Manufacturer: Micron

Device and Array Organization
Figure 10: Array Organization – MT29F4G08 (x8)
Table 6: Array Addressing – MT29F4G08 (x8)
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
Second
Fourth
Cycle
Third
Fifth
First
Cache Register
Data Register
2048 blocks
4096 blocks
per device
per plane
BA15
LOW
LOW
CA7
BA7
I/07
(0, 2, 4, 6, ..., 4092, 4094)
Notes:
even-numbered blocks
Plane of
2048
2048
1 block
1. Block address concatenated with page address = actual page address. CAx = column ad-
2. If CA11 is 1, then CA[10:6] must be 0.
3. BA6 controls plane selection.
BA14
LOW
LOW
I/06
CA6
BA6
dress; PAx = page address; BAx = block address.
2112 bytes
64
64
BA13
LOW
LOW
I/05
CA5
PA5
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
(1, 3, 5, 7, ..., 4093, 4095)
odd-numbered blocks
2048
2048
1 block
Plane of
2112 bytes
BA12
LOW
LOW
CA4
I/04
PA4
25
64
64
Micron Technology, Inc. reserves the right to change products or specifications without notice.
CA11
BA11
LOW
CA3
I/03
PA3
1 page
1 block
1 plane
1 device = 2112Mb x 2 planes
Device and Array Organization
DQ0
DQ7
= (2K + 64 bytes)
= (2K + 64) bytes x 64 pages
= (128K + 4K) bytes
= (128K + 4K) bytes x 2048 blocks
= 2112Mb
= 4224Mb
CA10
BA10
LOW
I/02
CA2
PA2
© 2009 Micron Technology, Inc. All rights reserved.
BA17
I/01
CA1
CA9
PA1
BA9
BA16
CA0
CA8
BA8
I/00
PA0