MT29C4G48MAZAPAKD-5 E IT Micron, MT29C4G48MAZAPAKD-5 E IT Datasheet - Page 9

• Manufacturer Part Number: MT29C4G48MAZAPAKD-5 E IT
• Manufacturer: Micron

Micron Confidential and Proprietary
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
Features
Figure 51: READ FOR INTERNAL DATA MOVE (00h-35h) Operation ............................................................... 83
Figure 52: READ FOR INTERNAL DATA MOVE (00h–35h) with RANDOM DATA READ (05h–E0h) ................... 83
Figure 53: INTERNAL DATA MOVE (85h-10h) with Internal ECC Enabled ....................................................... 84
Figure 54: INTERNAL DATA MOVE (85h-10h) with RANDOM DATA INPUT with Internal ECC Enabled ........... 84
Figure 55: PROGRAM FOR INTERNAL DATA MOVE (85h–10h) Operation ....................................................... 84
Figure 56: PROGRAM FOR INTERNAL DATA MOVE (85h-10h) with RANDOM DATA INPUT (85h) .................. 85
Figure 57: PROGRAM FOR INTERNAL DATA MOVE TWO-PLANE (85h-11h) Operation ................................... 85
Figure 58: Flash Array Protected: Invert Area Bit = 0 ........................................................................................ 87
Figure 59: Flash Array Protected: Invert Area Bit = 1 ........................................................................................ 87
Figure 60: UNLOCK Operation ...................................................................................................................... 88
Figure 61: LOCK Operation ............................................................................................................................ 89
Figure 62: LOCK TIGHT Operation ................................................................................................................ 90
Figure 63: PROGRAM/ERASE Issued to Locked Block ..................................................................................... 91
Figure 64: BLOCK LOCK READ STATUS ......................................................................................................... 91
Figure 65: BLOCK LOCK Flowchart ................................................................................................................ 92
Figure 66: OTP DATA PROGRAM (After Entering OTP Operation Mode) .......................................................... 95
Figure 67: OTP DATA PROGRAM Operation with RANDOM DATA INPUT (After Entering OTP Operation
Mode) ........................................................................................................................................................ 96
Figure 68: OTP DATA PROTECT Operation (After Entering OTP Protect Mode) ................................................ 97
Figure 69: OTP DATA READ .......................................................................................................................... 98
Figure 70: OTP DATA READ with RANDOM DATA READ Operation ................................................................ 99
Figure 71: TWO-PLANE PAGE READ ............................................................................................................. 101
Figure 72: TWO-PLANE PAGE READ with RANDOM DATA READ .................................................................. 102
Figure 73: TWO-PLANE PROGRAM PAGE ..................................................................................................... 102
Figure 74: TWO-PLANE PROGRAM PAGE with RANDOM DATA INPUT ......................................................... 103
Figure 75: TWO-PLANE PROGRAM PAGE CACHE MODE .............................................................................. 104
Figure 76: TWO-PLANE INTERNAL DATA MOVE .......................................................................................... 105
Figure 77: TWO-PLANE INTERNAL DATA MOVE with TWO-PLANE RANDOM DATA READ ........................... 106
Figure 78: TWO-PLANE INTERNAL DATA MOVE with RANDOM DATA INPUT .............................................. 107
Figure 79: TWO-PLANE BLOCK ERASE ......................................................................................................... 108
Figure 80: TWO-PLANE/MULTIPLE-DIE READ STATUS Cycle ....................................................................... 108
Figure 81: Spare Area Mapping (x8) ............................................................................................................... 112
Figure 82: Spare Area Mapping (x16) ............................................................................................................. 113
Figure 83: RESET Operation ......................................................................................................................... 122
Figure 84: READ STATUS Cycle ..................................................................................................................... 122
Figure 85: READ STATUS ENHANCED Cycle ................................................................................................. 123
Figure 86: READ PARAMETER PAGE ............................................................................................................. 123
Figure 87: READ PAGE ................................................................................................................................. 124
Figure 88: READ PAGE Operation with CE# “Don’t Care” ............................................................................... 125
Figure 89: RANDOM DATA READ ................................................................................................................. 126
Figure 90: READ PAGE CACHE SEQUENTIAL ................................................................................................ 127
Figure 91: READ PAGE CACHE RANDOM ..................................................................................................... 128
Figure 92: READ ID Operation ...................................................................................................................... 129
Figure 93: PROGRAM PAGE Operation .......................................................................................................... 129
Figure 94: PROGRAM PAGE Operation with CE# “Don’t Care” ....................................................................... 130
Figure 95: PROGRAM PAGE Operation with RANDOM DATA INPUT ............................................................. 130
Figure 96: PROGRAM PAGE CACHE .............................................................................................................. 131
Figure 97: PROGRAM PAGE CACHE Ending on 15h ....................................................................................... 131
Figure 98: INTERNAL DATA MOVE ............................................................................................................... 132
Figure 99: INTERNAL DATA MOVE (85h-10h) with Internal ECC Enabled ...................................................... 132
Figure 100: INTERNAL DATA MOVE (85h-10h) with Random Data Input with Internal ECC Enabled .............. 133
Figure 101: ERASE BLOCK Operation ............................................................................................................ 133
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168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
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