MT29C4G48MAZAPAKD-5 E IT Micron, MT29C4G48MAZAPAKD-5 E IT Datasheet - Page 43

• Manufacturer Part Number: MT29C4G48MAZAPAKD-5 E IT
• Manufacturer: Micron

Reset Operations
RESET (FFh)
Figure 26: RESET (FFh) Operation
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
The RESET command is used to put the memory device into a known condition and to
abort the command sequence in progress.
READ, PROGRAM, and ERASE commands can be aborted while the device is in the busy
state. The contents of the memory location being programmed or the block being
erased are no longer valid. The data may be partially erased or programmed, and is inva-
lid. The command register is cleared and is ready for the next command. The data
register and cache register contents are marked invalid.
The status register contains the value E0h when WP# is HIGH; otherwise it is written
with a 60h value. R/B# goes LOW for
command register.
The RESET command must be issued to all CE#s as the first command after power-on.
The device will be busy for a maximum of 1ms.
Cycle type
I/O[7:0]
R/B#
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
Command
FF
43
t
RST after the RESET command is written to the
t
WB
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
RST
© 2009 Micron Technology, Inc. All rights reserved.
Reset Operations