MT29C4G48MAZAPAKD-5 E IT Micron, MT29C4G48MAZAPAKD-5 E IT Datasheet - Page 170

• Manufacturer Part Number: MT29C4G48MAZAPAKD-5 E IT
• Manufacturer: Micron

Figure 111: Initialize and Load Mode Registers
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
Command
BA0, BA1
Address
V
DQS
V
CK#
CKE
A10
DDQ
DM
DQ
CK
DD
1
HIGH LEVEL
LVCMOS
Power-up: V
Notes:
NOP 2
T = 200µs
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DD
1. PRE = PRECHARGE command; LMR = LOAD MODE REGISTER command; AR = AUTO RE-
2. NOP or DESELECT commands are required for at least 200μs.
3. Other valid commands are possible.
4. NOPs or DESELECTs are required during this time.
and CK stable
t
IS
FRESH command; ACT = ACTIVE command.
NOP
T0
High-Z
High-Z
t
IH
t
CH
t
CK
t
CL
All banks
t
IS
PRE
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
T1
t
IH
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RP
4
AR
Ta0
170
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4
Tb0
AR
Micron Technology, Inc. reserves the right to change products or specifications without notice.
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Load standard
mode register
4
t
t
t
Op-code
Op-code
BA0 = L,
IS
IS
IS
BA1 = L
Tc0
LMR
t
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t
IH
IH
IH
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Load extended
mode register
4
Op-code
Op-code
BA0 = L,
BA1 = H
LMR
Td0
© 2009 Micron Technology, Inc. All rights reserved.
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MRD
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4
ACT
Te0
Row
Bank
Row
Initialization
3
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Don’t Care
NOP
Tf0
3