QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 10

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

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Internal Graphics Device 2 Configuration Register (D2:F0-F1) ............................... 273
8.1
8.2
7.2.9
7.2.10 LE1D - Link Entry 1 Description .............................................................. 269
7.2.11 LE1A - Link Entry 1 Address ................................................................... 270
7.2.12 PEGTC - PCI Express-G Timeout Control .................................................. 270
7.2.13 PEGCC - PCI Express-G Countdown Control .............................................. 271
7.2.14 PEGSTS - PCI Express-G Status .............................................................. 271
Device 2 Function 0 PCI Configuration Register Details.......................................... 273
8.1.1
8.1.2
8.1.3
8.1.4
8.1.5
8.1.6
8.1.7
8.1.8
8.1.9
8.1.10 MMADR - Memory Mapped Range Address................................................ 281
8.1.11 IOBAR - I/O Base Address...................................................................... 282
8.1.12 GMADR - Graphics Memory Range Address............................................... 283
8.1.13 GTTADR - Graphics Translation Table Range Address ................................. 283
8.1.14 SVID2 - Subsystem Vendor Identification................................................. 284
8.1.15 SID2 - Subsystem Identification ............................................................. 284
8.1.16 ROMADR - Video BIOS ROM Base Address................................................ 285
8.1.17 CAPPTR - Capabilities Pointer ................................................................. 285
8.1.18 INTRLINE - Interrupt Line ...................................................................... 286
8.1.19 INTRPIN - Interrupt Pin ......................................................................... 286
8.1.20 MINGNT - Minimum Grant ...................................................................... 286
8.1.21 MAXLAT - Maximum Latency .................................................................. 287
8.1.22 MCAPPTR - Mirror of Dev0 Capability Pointer ............................................ 287
8.1.23 MGGC - Mirror of Dev0 (G)MCH Graphics Control ...................................... 288
8.1.24 MDEVENdev0F0 - Mirror of Dev0 DEVEN .................................................. 289
8.1.25 BSM - Base of Stolen Memory................................................................. 290
8.1.26 MSAC - Multi Size Aperture Control ......................................................... 290
8.1.27 CAPL - Capabilities List Control ............................................................... 291
8.1.28 GDRST - Graphics Debug Reset .............................................................. 291
8.1.29 Unit Power Management Control4- UPMC4 ............................................... 292
8.1.30 PMCAPID - Power Management Capabilities ID.......................................... 292
8.1.31 PMCAP - Power Management Capabilities ................................................. 293
8.1.32 PMCS - Power Management Control/Status............................................... 294
8.1.33 SWSMI - Software SMI .......................................................................... 295
8.1.34 ASLE - System Display Event Register ..................................................... 296
8.1.35 GCFC - Graphics Clock Frequency Control ................................................ 296
8.1.36 ASLS - ASL Storage .............................................................................. 298
Device 2 Function 1 PCI Configuration Registers .................................................. 298
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
8.2.8
8.2.9
ESD - Element Self Description ............................................................... 268
VID2 - Vendor Identification ................................................................... 275
DID2 - Device Identification ................................................................... 275
PCICMD2 - PCI Command ...................................................................... 275
PCISTS2 - PCI Status ............................................................................ 277
RID2 - Revision Identification ................................................................. 278
CC - Class Code.................................................................................... 279
CLS - Cache Line Size............................................................................ 279
MLT2 - Master Latency Timer ................................................................. 280
HDR2 - Header Type ............................................................................. 280
VID2 - Vendor Identification ................................................................... 300
DID2 - Device Identification ................................................................... 300
PCICMD2 - PCI Command ...................................................................... 301
PCISTS2 - PCI Status ............................................................................ 302
RID2 - Revision Identification ................................................................. 303
CC - Class Code Register ....................................................................... 303
CLS - Cache Line Size............................................................................ 304
MLT2 - Master Latency Timer ................................................................. 304
HDR2 - Header Type ............................................................................. 305
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