QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 292

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

8.1.29
8.1.30
292
Unit Power Management Control4- UPMC4
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
PMCAPID - Power Management Capabilities ID
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
15:8
7:0
Bit
Bit
0
Access
Access
R/W
RO
RO
Default
Default
Value
Value
0b
00h
01h
Graphics Debug Reset:
Render and Display clock domain resets should be asserted for at
least 20 µs.
Once this bit is set to a 1 all GFX core MMIO registers are returned
to power on default state. All Ring buffer pointers are reset,
command stream fetches are dropped and ongoing render pipeline
processing is halted, state machines and State Variables returned
to power on default state, Display and overlay engines are halted
(garbage on screen). VGA memory is not available, Store dwords,
interrupts are not guaranteed to be completed. Device 2 IO
registers are not available.
Device 2 configuration registers are available when Graphics
debug reset is asserted.
NEXT_PTR:
This contains a pointer to next item in capabilities list. This is the
final capability in the list and must be set to 00h.
CAP_ID:
SIG defines this ID is 01h for power management.
1 = Assert display and render domain reset
0 = Deassert display and render domain reset
Internal Graphics Device 2 Configuration Register (D2:F0-F1)
0/2/0/PCI
C1-C2h
0000h
RO; R/W;
16 bits
0/2/0/PCI
D0-D1h
0001h
RO
16 bits
Description
Description
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