QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 125

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

Device 0 Memory Mapped I/O Register
Datasheet
31:28
27:24
Bit
Access
R/W
R/W
Default
Value
Bh
9h
Back-to-Back Write to Precharge Command Spacing
(Same Bank):
This field determines the number of clocks between write
command and a subsequent precharge command to the same
bank.
The minimum number of clocks is calculated based on this
formula for DDR2:
DDR2: CL - 1 + BL/2 + t WR
0h to 3h: Reserved
4h to Fh: Allowed
Write Recovery time (tWR).
Write recovery time is a standard DDR2 timing parameter that
determines minimum time between a write command and a
subsequent precharge command to the same bank. This
parameter is programmable on DDR2 DIMMs and the value
used above must match the largest delay programmed in any
DIMM in the system.
Minimum recommended values are documented below:
tWR (on CK)
3 Clocks: DDR2 400
4 Clocks: DDR2 533
5 Clocks: DDR2 667
Back-to-Back Write to Read Command Spacing (Same
Rank):
This field determines the number of clocks between write
command and a subsequent read command to the same rank.
The minimum number of clocks is calculated based on this
formula:
DDR2: CL - 1 + BL/2 + t WTR
0h - 5h: Reserved
6h - Ch: Allowed
Dh - Fh: Reserved
Write to Read Command delay (tWTR).
The tWTR is a standard DDR2 timing parameter and is used to
time a RD command after a WR command to the same row.
Following are the values used for tWTR
2 Clocks – DDR2 400 or DDR2 533
3 Clocks – DDR2 667
(Sheet 1 of 4)
Description
125