QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 395

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

Functional Description
Note:
10.8
10.8.1
10.8.2
Datasheet
When process shrinks or other power optimizations occur and current/power
dissipation decreases, the system can use this knowledge to optimize power/thermal
management and regain system performance. DT in SPD is a JEDEC Standard for DDR2
memory
For accurate VTS operation, DRAM modules need to implement DT in SPD. In the event
of DRAM modules not having DT information in SPD, the (G)MCH shall rely on the
settings programmed by BIOS to the event weight registers during memory
initialization.
Clocking
Overview
The (G)MCH has a total of 4 PLLs which is used for many internal clocks. The PLLs are:
(G)MCH Reference Clocks
HCLKP / HCLKN
DREF_CLKN / DREF_CLKP
DREF_SSCCLKN / DREF_SSCCLKP
GCLKP / GCLKN
• Host PLL – Generates the main core clocks in the host clock domain. Can also be
• PCI Express PLL – Generates all PCI Express related clocks, including the DMI that
• Display PLL A – Generates the internal clocks for Display A. Uses the low voltage 96
• Display PLL B – Generates the internal clocks for Display A or Display B. Uses the
used to generate memory and internal graphics core clocks. Uses the host clock
(HCLKN/HCLKP) as a reference.
connects to the ICH. This PLL uses the 100 MHz (GCLKN/GCLKP) as a reference.
MHz differential clock, DREF_CLKIN, as a reference.
low voltage 96 MHz differential clock, DREF_CLKIN, as a reference. Also may
optionally use DREF_SSCCLKIN as a reference for SSC support for LVDS display on
pipe B.
Reference Input Clocks
133 MHz / 166 MHz
96 MHz
96 MHz (non-SSC)/
100 MHz (SSC)
100 MHz
Input Frequency
Host / Memory / Graphics Core
Display PLL B
PCI Express* / DMI PLL
Display PLL A
Associated PLL
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