QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 132

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

6.2.15
6.2.16
132
C0DRT2 - Channel 0 DRAM Timing Register 2
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
C0DRC0 - Channel 0 DRAM Controller Mode 0
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
31:30
29:18
17:16
15:11
31:30
27:24
10:8
7:0
Bit
Bit
29
28
Access
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
Default
Value
Default
01b
Value
0b
0b
0h
000h
011b
111b
10b
00b
00h
Reserved
Initialization Complete (IC):
This bit is used for communication of software state between the
memory controller and the BIOS. BIOS sets this bit to 1 after
initialization of the DRAM memory array is complete.
Reserved
Active SDRAM Ranks:
Implementations may use this field to limit the maximum number
of SDRAM ranks that may be active at once.
0000: All ranks allowed to be in the active state
0001: One Rank
0010: Two Ranks
Others: Reserved
CKE Deassert Duration:
00 = 1 Mcclk
01 = Reserved
10 = 3 Mcclk (DDR 2)
11 = Reserved
Must be set to 10 for DDR2
Reserved
Reserved
Reserved
Reserved
Reserved
0/0/0/MCHBAR
118-11Bh
800003FFh
R/W; RO
32 bits
0/0/0/MCHBAR
120-123h
40000802h
R/W; RO
32 bits
(Sheet 1 of 4)
Description
Description
Device 0 Memory Mapped I/O Register
Datasheet