QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 89

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

Host Bridge Device 0 - Configuration Registers (D0:F0)
5.1.13
Datasheet
MCHBAR - (G)MCH Memory Mapped Register Range Base
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This is the base address for the MCH MMIO Configuration space. There is no physical
memory within this 16-KB window that can be addressed. The 16 KB reserved by this
register does not alias to any conventional PCI 2.3-compliant memory mapped space.
On reset, this register is disabled and must be enabled by writing a 1 to bit[0] of this
register.
31:14
13:1
Bit
0
Access
R/W/L
R/W/L
RO
Default
00000h
0000h
Value
0b
(G)MCH Memory Map Base Address:
This field corresponds to bits 31 to 14 of the base address
MCHBAR configuration space.
BIOS will program this register resulting in a base address for a
16-KB block of contiguous memory address space. This register
ensures that a naturally aligned 16-KB space is allocated within
total addressable memory space of 4 GB.
System Software uses this base address to program the MCH
register set.
Reserved
MCHBAR Enable (MCHBAREN):
0: MCHBAR is disabled and does not claim any memory.
1: MCHBAR memory mapped accesses are claimed and decoded
appropriately.
0/0/0/PCI
44-47h
00000000h
R/W/L; RO
32 bits
Description
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