QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 238

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

Note:
7.1.17
238
Configuration software is responsible for programming all address range registers
(prefetchable, non-prefetchable) with the values that provide exclusive address ranges,
i.e., prevent overlap with each other and/or with the ranges covered with the main
memory. There is no provision in the (G)MCH hardware to enforce prevention of
overlap and operations of the system in the case of overlap are not guaranteed.
PMBASE1 - Prefetchable Memory Base Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register in conjunction with the corresponding Upper Base Address register
controls the CPU to PCI Express-G prefetchable memory access routing based on the
following formula:
PREFETCHABLE_MEMORY_LIMIT
The upper 12 bits of this register are read/write and correspond to address bits
A[31:20] of the 32-bit address. This register must be initialized by the configuration
software. For the purpose of address decode address bits A[19:0] are assumed to be 0.
Thus, the bottom of the defined memory address range will be aligned to a 1-MB
boundary.
15:4
15:4
3:0
3:0
Bit
Bit
PREFETCHABLE_MEMORY_BASE <= address <=
Access
Access
R/W
R/W
RO
RO
Default
Default
Value
Value
000h
FFFh
0h
0h
Memory Address Limit (MLIMIT):
Corresponds to A[31:20] of the upper limit of the address range
passed to PCI Express-G*.
Reserved
Prefetchable Memory Base Address (MBASE):
Corresponds to A[31:20] of the lower limit of the memory range
that will be passed to PCI Express-G*.
Reserved
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
0/1/0/PCI
24-25h
FFF1h
R/W; RO
16 bits
Description
Description
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