QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 35

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

Signal Description
2
Note:
Datasheet
Signal Description
This section describes the (G)MCH signals. These signals are arranged in functional
groups according to their associated interface. The following notations are used to
describe the signal type:
The signal description also includes the type of buffer used for the particular signal:
System Address and Data Bus signals are logically inverted signals. The actual values
are inverted of what appears on the system bus. This must be considered and the
addresses and data bus signals must be inverted inside the (G)MCH. All processor
control signals follow normal convention: A 0 indicates an active level (low voltage),
and a 1 indicates an active level (high voltage).
I
O
I/O
AGTL+
PCI Express*
CMOS
HVCMOS
COD
SSTL-1.8
A
LVDS
Ref
Notations
Input pin
Output pin
Bi-directional Input/Output pin
Open Drain AGTL+ interface signal. Refer to the AGTL+ I/O Specification for
complete details. (V
PCI Express interface signals. These signals are compatible with current PCI
Local Bus Specification Signaling Environment AC Specifications. The buffers
are not 3.3 V tolerant. Differential voltage spec = (|D+ - D-|) * 2 = 1.2 V max.
Single-ended maximum = 1.5 V.
Single-ended minimum = 0 V. Please refer to the PCI Local Bus Specification.
CMOS buffers. 1.5-V tolerant
CMOS buffers. 3.3-V tolerant
CMOS Open Drain buffers. 3.3-V tolerant
Stub Series Termination Logic: These are 1.8-V capable buffers. 1.8-V tolerant
Analog reference or output. May be used as a threshold voltage or for buffer
compensation.
Low Voltage Differential signal interface
Voltage reference signal
Signal Type
CCP
)
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