QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 51

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

Signal Description
2.6
Datasheet
PLL Signals
LDDC_DATA
SDVOCTRL_CLK
SDVOCTRL_DATA
CLK_REQ#
HCLKP
HCLKN
GCLKP
GCLKN
DREF_CLKP
DREF_CLKN
DREF_SSCLKP
DREF_SSCLKN
Signal Name
Signal Name
Diff Clk
Diff Clk
Diff Clk
Diff Clk
Diff Clk
Diff Clk
Diff Clk
Diff Clk
Type
COD
O
I
I
I
I
I
I
I
I
Type
COD
COD
COD
I/O
I/O
I/O
External Clock Request:
(G)MCH drives CLK_REQ# to control the PCI Express*
differential clock input to itself.
Not supported with the Intel® 915 Express Chipset family
clocking solutions.
Differential Host Clock In:
Differential clock input for the host PLL. This is a low voltage
differential signal and runs at the FSB data rate.
Differential Host Clock Input Complement
Differential PCI Express-Based Graphics / DMI Clock In:
These pins receive a differential 100-MHz Serial Reference clock
from the external clock synthesizer. This clock is used to
generate the clocks necessary for the support of PCI Express.
Differential PCI Express Based Graphics / DMI Clock In
Complement
Display PLLA Differential Clock In – 96 MHz:
Display PLL Differential Clock In, no SSC support
Display PLLA Differential Clock In Complement:
Display PLL Differential Clock In Complement - no SSC support.
Display PLLB Differential Clock In – 100 MHz:
Optional Display PLL Differential Clock In for SSC support.
Note: Differential Clock input for optional SSC support for LVDS
display.
Display PLLB Differential Clock In Complement:
Optional Display PLL Differential Clock In Complement for SSC
support
Note: Differential Clock input for optional SSC support for LVDS
display.
EDID support for flat panel display
I
I
2
2
C-based control signal (Clock) for SDVO device
C-based control signal (Data) for SDVO device
Description
Description
51