QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 149

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

Device 0 Memory Mapped I/O Register
6.2.43
6.2.44
6.2.45
Datasheet
C1DTO - Channel 1 Throttling Observation
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register enables observation of the state of the throttling mechanism and current
measured bandwidth information.
C1DTC - Channel 1 DRAM Throttling Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
The operation of this register is detailed in the description for register C0DTC.
C1DMC - Channel 1 DRAM Maintenance Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
The register fields allow control of DRAM and MCH ODT.
31:20
19:19
18:16
15:8
7:0
Bit
Access
R/W
RO
RO
RO
RO
Default
Value
000h
000b
00h
N/A
0b
Reserved
Reserved
Filter Average Selector:
000 = (G)MCH Filter Average
001 = Rank 0 Filter Average
010 = Rank 1 Filter Average
011-111 = Reserved
Selected Filter Average
(G)MCH and DRAM Throttling Control Signals
0/0/0/MCHBAR
1DC-1DFh
000000_xxxx__xxxx_h
R/W; RO
32 bits
0/0/0/MCHBAR
1D8-1DBh
00000000h
R/W/L; RO
32 bits
0/0/0/MCHBAR
1E4-1E7h
00000020h
R/W; RO
32 bits
Description
149