QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 105

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

Host Bridge Device 0 - Configuration Registers (D0:F0)
5.1.28
Note:
Datasheet
ESMRAMC - Extended System Management RAM Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
The Extended SMRAM register controls the configuration of Extended SMRAM space.
The Extended SMRAM (E_SMRAM) memory provides a write-back cacheable SMRAM
memory space that is above 1 MB.
When Extended SMRAM is used, the maximum amount of DRAM accessible is limited to
256 MB.
2:0
Bit
Bit
7
6
5
4
Access
Access
R/W/L
R/WC
RO
RO
RO
Default
Default
Value
Value
010b
0b
0b
1b
1b
Compatible SMM Space Base Segment (C_BASE_SEG):
This field indicates the location of SMM space. SMM DRAM is not
remapped. It is simply made visible if the conditions are right to
access SMM space, otherwise the access is forwarded to DMI.
Since the MCH supports only the SMM space between A0000 and
BFFFF, this field is hardwired to 010.
Enable High SMRAM (H_SMRAME):
Controls the SMM memory space location (i.e., above 1 MB or
below 1 MB) When G_SMRAME is 1 and H_SMRAME this bit is set
to 1, the high SMRAM memory space is enabled.
SMRAM accesses within the range 0FEDA0000h to 0FEDBFFFFh
are remapped to DRAM addresses within the range 000A0000h to
000BFFFFh.
Once D_LCK has been set, this bit becomes read only.
Invalid SMRAM Access (E_SMERR):
This bit is set when CPU has accessed the defined memory
ranges in Extended SMRAM (High Memory and T-segment) while
not in SMM space and with the D-OPEN bit = 0. It is software’s
responsibility to clear this bit.
The software must write a 1 to this bit to clear it.
SMRAM Cacheable (SM_CACHE):
This bit is forced to 1 by the MCH.
L1 Cache Enable for SMRAM (SM_L1):
This bit is forced to 1 by the MCH.
0/0/0/PCI
9Eh
38h
R/W/L; R/WC; RO
8 bits
(Sheet 1 of 2)
Description
Description
105