QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 5

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

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Datasheet
Device 0 Memory Mapped I/O Register.................................................................. 113
6.1
6.2
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
5.1.7
5.1.8
5.1.9
5.1.10 PAGE BREAKSID - Subsystem Identification ............................................... 87
5.1.11 CAPPTR - Capabilities Pointer ................................................................... 87
5.1.12 EPBAR - Egress Port Base Address ............................................................ 88
5.1.13 MCHBAR - (G)MCH Memory Mapped Register Range Base ............................ 89
5.1.14 PCIEXBAR - PCI Express Register Range Base Address ................................ 90
5.1.15 DMIBAR - MCH-ICH Serial Interconnect Ingress Root Complex ..................... 92
5.1.16 GGC - (G)MCH Graphics Control (Device 0)................................................ 93
5.1.17 DEVEN - Device Enable ........................................................................... 94
5.1.18 PAM0 - Programmable Attribute Map 0 ...................................................... 95
5.1.19 PAM1 - Programmable Attribute Map 1 ...................................................... 96
5.1.20 PAM2 - Programmable Attribute Map 2 ...................................................... 97
5.1.21 PAM3 - Programmable Attribute Map 3 ...................................................... 98
5.1.22 PAM4 - Programmable Attribute Map 4 ...................................................... 99
5.1.23 PAM5 - Programmable Attribute Map 5 .................................................... 100
5.1.24 PAM6 - Programmable Attribute Map 6 .................................................... 101
5.1.25 LAC - Legacy Access Control .................................................................. 102
5.1.26 TOLUD - Top of Low Used DRAM Register ................................................ 103
5.1.27 SMRAM - System Management RAM Control............................................. 104
5.1.28 ESMRAMC - Extended System Management RAM Control ........................... 105
5.1.29 TOM - Top Of Memory........................................................................... 106
5.1.30 ERRSTS - Error Status .......................................................................... 107
5.1.31 ERRCMD - Error Command .................................................................... 108
5.1.32 SKPD - Scratchpad Data........................................................................ 109
5.1.33 CAPID0 - Capability Identifier ................................................................ 109
Device 0 Memory Mapped I/O Registers ............................................................. 113
Device 0 MCHBAR Chipset Control Registers........................................................ 113
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
6.2.9
6.2.10 C0DRA2 - Channel 0 DRAM Rank 2,3 Attribute ......................................... 122
6.2.11 C0DCLKDIS - Channel 0 DRAM Clock Disable ........................................... 122
6.2.12 C0BNKARC - Channel 0 DRAM Bank Architecture ...................................... 123
6.2.13 C0DRT0 - Channel 0 DRAM Timing Register 0........................................... 124
6.2.14 C0DRT1 - Channel 0 DRAM Timing Register 1........................................... 129
6.2.15 C0DRT2 - Channel 0 DRAM Timing Register 2........................................... 132
6.2.16 C0DRC0 - Channel 0 DRAM Controller Mode 0 .......................................... 132
6.2.17 C0DRC1 - Channel 0 DRAM Controller Mode 1 .......................................... 135
6.2.18 C0DRC2 - Channel 0 DRAM Controller Mode 2 .......................................... 136
VID - Vendor Identification ...................................................................... 81
DID - Device Identification ...................................................................... 81
PCICMD - PCI Command ......................................................................... 81
PCISTS - PCI Status ............................................................................... 83
RID - Revision Identification .................................................................... 84
CC - Class Code ..................................................................................... 85
MLT - Master Latency Timer..................................................................... 85
HDR - Header Type................................................................................. 86
SVID - Subsystem Vendor Identification .................................................... 86
FSBPMC3 Front Side Bus Power Management Control 3 ............................. 118
FSBPMC4 Front Side Bus Power Management Control 4 ............................. 118
FSBSNPCTL- FSB Snoop Control ............................................................. 118
SLPCTL – CPU Sleep Timing Control ........................................................ 118
C0DRB0 - Channel 0 DRAM Rank Boundary 0 ........................................... 119
C0DRB1 - Channel 0 DRAM Rank Boundary 1 ........................................... 119
C0DRB2 - Channel 0 DRAM Rank Boundary 1 ........................................... 120
C0DRB3 - Channel 0 DRAM Rank Boundary 1 ........................................... 120
C0DRA0 - Channel 0 DRAM Rank 0,1 Attribute ......................................... 121
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