QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 379

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

Functional Description
Figure 23.
10.5.4.2.4
10.5.4.2.5
10.5.4.2.6
10.5.4.2.7
10.5.4.3
Datasheet
LVDS Clock and Data Relationship
LVDS Pair States
The LVDS pairs can be put into one of five states, powered down tri-state, powered
down 0 V, common mode, send 0’s, or active. When in the active state, several data
formats are supported. When in powered down state, the circuit enters a low power
state and drives out 0 V or tri-states on both the output pins for the entire channel. The
common mode tri-state is both pins of the pair set to the common mode voltage. These
are the signals that optionally get used when driving either 18-bpp panels or dual-
channel with a single clock. When in the send 0’s state, the circuit is powered up but
sends only 0 for the pixel color data regardless what the actual data is with the clock
lines and timing signals sending the normal clock and timing data.
Single-channel versus Dual-channel Mode
Both Single-channel and Dual-channel modes are available to allow interfacing to either
Single- or Dual-channel panel interfaces. This LVDS port can operate in Single-channel
or Dual-channel mode. Dual-channel mode uses twice the number of LVDS pairs and
transfers the pixel data at twice the rate of the single-channel. In general, one channel
will be used for even pixels and the other for odd pixel data. The first pixel of the line is
determined by the display enable going active and that pixel will be sent out channel A.
All horizontal timings for active, sync, and blank will be limited to be on two pixel
boundaries in the two channel modes.
LVDS Channel Skew
When in Dual-channel mode, the two channels must meet the panel requirements with
respect to the inter channel skew.
LVDS PLL
The Display PLL is used to synthesize the clocks that control transmission of the data
across the LVDS interface. The three operations that are controlled are the pixel rate,
the load rate, and the IO shift rate. These are synchronized to each other and have
specific ratios based on Single-channel or Dual-channel mode. If the pixel clock is
considered the 1x rate, a 7x or 3.5 speeds IO_shift clock needed for the high speed
serial outputs setting the data rate of the transmitters. The load clock will have either a
1x or 0.5x ratio to the pixel clock.
Panel Power Sequencing
This section provides details for the power sequence timing relationship of the panel
power, the backlight enable and the LVDS data timing delivery. In order to meet the
panel power timing specification requirements, two signals, PANELVDDEN and
PANELBKLTEN are provided to control the timing sequencing function of the panel and
the backlight power supplies.
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