QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 140

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

6.2.23
6.2.24
140
C0DTAEW - Channel 0 Dram Rank Throttling Active Event
Weights
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register contains programmable Event weights that are input into the averaging
filter. Each Event weight is a normalized 8-bit value that the BIOS must program. The
BIOS must account for burst length considerations. It is also possible for BIOS to take
into account loading variations caused by different memory types and population of
ranks. The (G)MCH sends a command to the selected DRAM (via CS# assertion). Based
on the command type, one of the weights specified in this register is added to the
weight specified in the previous register, which is then input to the filter.
C0DTC - Channel 0 Dram Throttling Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register is for Programmable Event weights that are inputs into the averaging filter.
Each Event weight is a normalized 8-bit value that the BIOS must program. The BIOS
must account for burst length, 1N/2N rule considerations. It is also possible for bios to
take into account type loading variations of memory caused as a function of memory
types and population of ranks.
63:56
55:48
47:40
39:32
31:24
23:16
15:8
7:0
Bit
Access
R/W/L
R/W/L
R/W/L
R/W/L
R/W/L
R/W/L
R/W/L
R/W/L
Default
Value
00h
00h
00h
00h
00h
00h
00h
00h
Read with AP
Write with AP
Read
Write
Precharge - All
Precharge
Activate
Refresh
0/0/0/MCHBAR
150-157h
0000000000000000h
R/W/L
64 bits
0/0/0/MCHBAR
158-15Bh
00000000h
R/W/L; RO
32 bits
Description
Device 0 Memory Mapped I/O Register
Datasheet