QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 276

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

276
15:11
Bit
10
9
8
7
6
5
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
RO
RO
Default
Value
00h
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
Reserved
Interrupt Disable:
This bit disables the device from asserting INTx#.
DO_INTx messages will not be sent to DMI.
Fast Back-to-Back (FB2B):
Not Implemented. Hardwired to 0.
SERR Enable (SERRE):
Not Implemented. Hardwired to 0.
Address/Data Stepping Enable (ADSTEP):
Not Implemented. Hardwired to 0.
Parity Error Enable (PERRE):
Not Implemented. Hardwired to 0.
Since the IGD belongs to the category of devices that does not
corrupt programs or data in system memory or hard drives, the
IGD ignores any parity error that it detects and continues with
normal operation.
Video Palette Snooping (VPS):
This bit is hardwired to 0 to disable snooping.
Memory Write and Invalidate Enable (MWIE):
Hardwired to 0. The IGD does not support memory write and
invalidate commands.
Special Cycle Enable (SCE):
This bit is hardwired to 0. The IGD ignores Special cycles.
Bus Master Enable (BME):
Memory Access Enable (MAE):
This bit controls the IGD's response to memory space accesses.
I/O Access Enable (IOAE):
This bit controls the IGD's response to I/O space accesses.
0: Enable the assertion of this device’s INTx# signal.
1: Disable the assertion of this device’s INTx# signal.
0: Disable IGD bus mastering.
1: Enable the IGD to function as a PCI-compliant master.
0: Disable
1: Enable
0: Disable
1: Enable
Internal Graphics Device 2 Configuration Register (D2:F0-F1)
Description
Datasheet