QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 172
QG82945GSE S LB2R
Manufacturer Part Number
QG82945GSE S LB2R
Description
GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
Manufacturer
Intel
Datasheet
1.AU80586GE025DSLB73.pdf
(482 pages)
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6.4.3
6.4.4
172
TR1 - Thermometer Read1
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register generally provides the calibrated current temperature from the
thermometer circuit when the Thermometer mode is enabled.
TSTTP1 - Thermal Sensor Temperature Trip Point 1-1
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register:
31:24
23:16
• Sets the target values for some of the trip points in thermometer mode. See also
• Reports the relative thermal sensor temperature. See also TSTTP1-2
15:8
7:0
7:0
Bit
Bit
TST [Direct DAC Connect Test Enable].
Access
Access
R/W/L
R/W/L
R/W/L
RO
RO
Default
Default
Value
Value
FFh
00h
00h
00h
00h
Thermometer Reading (TR):
Provides the current counter value. The current counter value
corresponds to thermal sensor temperature if TSS
[Thermometer mode Output Valid] = 1.
This register has a straight binary encoding that will range from
0 to FFh.
Relative Temperature (RELT):
HTPS-TR. In Thermometer mode, the RELT field of this register
reports the relative temperature of the thermal sensor. Provides
a two's complement value of the thermal sensor relative to the
Hot trip point. Temperature above the Hot trip point will be
positive.
See also TSS [Thermometer mode Output Valid]
In the Analog mode, the RELT field reports HTPS value.
Aux0 Trip Point Setting (A0TPS):
Sets the target for the Aux0 trip point.
Lockable by TSTTP2-1 [31].
Hot Trip Point Setting (HTPS):
Sets the target value for the Hot trip point.
Lockable via TCO bit 7.
Catastrophic Trip Point Setting (CTPS):
Sets the target for the Catastrophic trip point.
Lockable via TCO bit 7.
0/0/0/MCHBAR
C8Bh
FFh
RO
8 bits
0/0/0/MCHBAR
C8C-C8Fh
00000000h
R/W/L; RO
32 bits
Description
Description
Device 0 Memory Mapped I/O Register
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