QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 237

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

PCI Express Graphics Device 1 Configuration Registers (D1:F0)
7.1.15
7.1.16
Note:
Datasheet
MBASE1 - Memory Base Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register controls the CPU to PCI Express-G non-prefetchable memory access
routing based on the following formula:
The upper 12 bits of the register are read/write and correspond to the upper 12
address bits A[31:20] of the 32-bit address. The bottom 4 bits of this register are read-
only and return 0’s when read. This register must be initialized by the configuration
software. For the purpose of address decode address bits A[19:0] are assumed to be 0.
Thus, the bottom of the defined memory address range will be aligned to a 1-MB
boundary.
MLIMIT1 - Memory Limit Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register controls the CPU to PCI Express-G non-prefetchable memory access
routing based on the following formula:
MEMORY_BASE=< address =<MEMORY_LIMIT
The upper 12 bits of the register are read/write and correspond to the upper 12
address bits A[31:20] of the 32-bit address. The bottom 4 bits of this register are read-
only and return 0’s when read. This register must be initialized by the configuration
software. For the purpose of address decode address bits A[19:0] are assumed to be
FFFFFh. Thus, the top of the defined memory address range will be at the top of a 1-MB
aligned memory block.
Memory range covered by MBASE and MLIMIT registers are used to map non-
prefetchable PCI Express-G address ranges (typically where control/status memory-
mapped I/O data structures of the graphics controller will reside) and PMBASE and
PMLIMIT are used to map prefetchable address ranges (typically graphics local
memory). This segregation allows application of USWC space attribute to be performed
in a true plug-and-play manner to the prefetchable address range for improved CPU-
PCI Express memory access performance.
MEMORY_BASE <= address <= MEMORY_LIMIT
15:4
3:0
Bit
Access
R/W
RO
Default
Value
FFFh
0h
Memory Address Base (MBASE):
Corresponds to A[31:20] of the lower limit of the memory range
that will be passed to PCI Express-G*.
Reserved
0/1/0/PCI
20-21h
FFF0h
R/W; RO
16 bits
0/1/0/PCI
22-23h
0000h
R/W; RO
16 bits
Description
237