QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 106

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

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TOM - Top Of Memory
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
2:1
Bit
3
0
Access
R/W/L
R/W/L
RO
Default
Value
00b
1b
0b
L2 Cache Enable for SMRAM (SM_L2):
This bit is forced to 1 by the MCH.
TSEG Size (TSEG_SZ):
Selects the size of the TSEG memory block if enabled. Memory
from the top of DRAM space is partitioned away so that it may
only be accessed by the processor interface and only then when
the SMM bit is set in the request packet. Non-SMM accesses to
this memory region are sent to DMI when the TSEG memory
block is enabled.
00 - 1-MB TSEG (TOLUD: Graphics Stolen Memory Size - 1 M) to
(TOLUD - Graphics Stolen Memory Size).
01 - 2-MB Tseg (TOLUD: Graphics Stolen Memory Size - 2 M) to
(TOLUD - Graphics Stolen Memory Size).
10 - 8-MB Tseg (TOLUD: Graphics Stolen Memory Size - 8 M) to
(TOLUD - Graphics Stolen Memory Size).
11 - Reserved
_LCK has been set, these bits become read only.
TSEG Enable (T_EN):
Enabling of SMRAM memory for Extended SMRAM space only.
When G_SMRAME =1 and TSEG_EN = 1, the TSEG is enabled to
appear in the appropriate physical address space.
Once D_LCK is set, this bit becomes read only.
0/0/0/PCI
A0-A1h
0001h
R/W/L; RO
16 bits
(Sheet 2 of 2)
Host Bridge Device 0 - Configuration Registers (D0:F0)
Description
Datasheet