QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 280

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QG82945GSE S LB2R

Manufacturer Part Number
QG82945GSE S LB2R
Description
GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
Manufacturer
Intel
Datasheet
8.1.8
8.1.9
280
MLT2 - Master Latency Timer
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
The IGD does not support the programmability of the master latency timer because it
does not perform bursts.
HDR2 - Header Type
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register contains the Header Type of the IGD.
7:0
7:7
6:0
Bit
Bit
Access
Access
RO
RO
RO
Default
Default
Value
Value
00h
00h
1b
Master Latency Timer Count Value:
Hardwired to 0’s.
Multi Function Status (MFunc):
Indicates if the device is a Multi-Function Device. The Value of
this register is determined by Device 0, offset 54h, DEVEN[4]. If
Device 0 DEVEN[4] is set, the MFunc bit is also set.
Header Code (H):
This is a 7-bit value that indicates the Header Code for the IGD.
This code has the value 00h, indicating a type 0 configuration
space format.
Internal Graphics Device 2 Configuration Register (D2:F0-F1)
0/2/0/PCI
Dh
00h
RO
8 bits
0/2/0/PCI
Eh
80h
RO
8 bits
Description
Description
Datasheet

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