QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 73

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

(G)MCH Configuration Process and Registers
Figure 7.
Datasheet
3
1
As with PCI devices, each device is selected based on decoded address information that
is provided as a part of the address portion of Configuration Request packets. A PCI
Express device will decode all address information fields (bus, device, function and
extended address numbers) to provide access to the correct register.
To access this space (steps 1, 2, 3 are done only once by BIOS):
PCI Express configuration writes:
See the current PCI Local Bus Specification for more information on both the
conventional PCI 2.3 compatible and PCI Express enhanced configuration mechanism
and transaction rules.
Memory Map to PCI Express Device Configuration Space
1. Use the PCI-compatible configuration mechanism to enable the PCI Express
2. Use the PCI-compatible configuration mechanism to write an appropriate PCI
3. Calculate the host address of the register you wish to set using (PCI Express base
4. Use a memory write or memory read cycle to the calculated host address to write
Base
• Internally the host interface unit will translate writes to PCI Express extended
• The host interface unit will treat the posted write as a non-posted write internal to
• Writes to extended space are posted on the FSB, but non-posted on the PEG or DMI
enhanced configuration mechanism by writing 1 to bit 31 of the DEVEN register.
Express base address into the PCIEXBAR register.
+ (bus number * 1 MB) + (device number * 32 KB) + (function number * 4 KB) +
(1 B * offset within the function) = host address).
to or read from that register.
configuration space to configurations on the backbone.
the host interface unit.
pins (i.e., translated to configuration writes).
2
8
2
7
0xFFFFFFF
PCI Express Base
0x1FFFFF
0xFFFFF
Located by
Address
0
Bus
Bus 255
Bus 1
Bus 0
2
0
0xFFFFF
0xFFFF
0x7FFF
1
9
Device 31
Device 1
Device 0
Device
1
5
0x7FFF
0x1FFF
0xFFF
1
4
Func.
Function 1
Function 0
1
2
1
1
Extended
0xFFF
0xFF
0x3F
8 7
Configuration
PCI Compatible
PCI Compatible
PCI Express
Space Header
Configuration
Configuration
Register Number x x
Extended
Space
Space
2 1 0
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