QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 310

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

8.2.19
8.2.20
310
MDEVENdev0F0 - Mirror of Dev0 DEVEN
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register allows for enabling/disabling of PCI devices and functions that are within
the MCH. This table describes the behavior of all combinations of transactions to
devices controlled by this register.
SSRW - Software Scratch Read Write
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
31:7
31:0
Bit
Bit
4
3
2
1
0
Access
Access
RO
RO
RO
RO
RO
RO
RO
0000000h Reserved
00000000h
Default
Default
Value
Value
1b
1b
0b
1b
1b
Internal Graphics Engine Function 1 (D2F1EN):
0: Bus 0 Device 2 Function 1 is disabled and hidden.
1: Bus 0 Device 2 Function 1 is enabled and visible.
Internal Graphics Engine Function 0 (D2F0EN):
0: Bus 0 Device 2 Function 0 is disabled and hidden.
1: Bus 0 Device 2 Function 0 is enabled and visible.
Reserved
PCI Express Graphics Port Enable (D1EN):
0: Bus 0 Device 1 Function 0 is disabled and hidden.
1: Bus 0 Device 1 Function 0 is enabled and visible.
Default value is determined by the device capabilities, SDVO
presence HW strap and SDVO/PCIe concurrent HW strap.
Device 1 is Disabled on Reset if {the SDVO present strap is
sampled high and the SDVO/PCIe concurrent strap is sampled
low}.
Host Bridge:
Bus 0 Device 0 Function 0 may not be disabled and is therefore
hardwired to 1.
Reserved
Internal Graphics Device 2 Configuration Register (D2:F0-F1)
0/2/1/PCI
54-57h
0000001Bh
RO
32 bits
0/2/1/PCI
58-5Bh
00000000h
RO
32 bits
Description
Description
Datasheet