QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 203

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

Device 0 Memory Mapped I/O Register
6.6.6
Datasheet
DMIVC0RCTL0 - DMI VC0 Resource Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register controls the resources associated with PCI Express Virtual Channel 0.
31:31
30:27
26:24
23:20
19:17
16:8
7:1
Bit
0
Access
R/W
R/W
RO
RO
RO
RO
RO
RO
Default
Value
000b
000b
000h
7Fh
1b
0h
0h
1b
Virtual Channel 0 Enable (VC0E):
For VC0 this is hardwired to 1 and read only as VC0 can never
be disabled.
Reserved
Virtual Channel 0 ID (VC0ID):
Assigns a VC ID to the VC resource. For VC0 this is hardwired
to 0 and read only.
Reserved
Port Arbitration Select (PAS):
Configures the VC resource to provide a particular Port
Arbitration service. Valid value for this field is a number
corresponding to one of the asserted bits in the Port Arbitration
Capability field of the VC resource. Because only bit 0 of that
field is asserted.
This field will always be programmed to 1.
Reserved
Traffic Class / Virtual Channel 0 Map (TCVC0M):
Indicates the TCs (Traffic Classes) that are mapped to the VC
resource. Bit locations within this field correspond to TC values.
For example, when bit 7 is set in this field, TC7 is mapped to
this VC resource. When more than one bit in this field is set, it
indicates that multiple TCs are mapped to the VC resource. In
order to remove one or more TCs from the TC/VC Map of an
enabled VC, software must ensure that no new or outstanding
transactions with the TC labels are targeted at the given link.
Traffic Class 0 / Virtual Channel 0 Map (TC0VC0M):
Traffic Class 0 is always routed to VC0.
0/0/0/DMIBAR
14-17h
800000FFh
R/W; RO
32 bits
Description
203