QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 183

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

Device 0 Memory Mapped I/O Register
6.4.15
Datasheet
TCO0 - Thermal Calibration Offset0
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
15:8
7:7
6:0
7:0
Bit
Bit
Access
Access
R/W/L
R/WO
R/W/L
R/W/L
Default
Default
Value
Value
00h
00h
00h
0b
Lock bit for Catastrophic (LBC):
This bit, when written to a 1, locks the Catastrophic
programming interface, including bits 7:0 of this register and
bits 7:0 of TSTTP1-0 [15-0], bits 1,7 of TSC 1 and 0 to 3 of TSC
2, and bits 0,7 of TST. This bit may only be set to a 0 by a
hardware reset. Writing a 0 to this bit has no effect.
Calibration Offset (CO):
This field contains the current calibration offset for the Thermal
Sensor DAC inputs. The calibration offset is a twos complement
signed number which is added to the temperature counter value
to help generate the final value going to the thermal sensor
DAC.
This field is Read/Write and can be modified by Software unless
locked by setting bit 7 of this register.
The fuses cannot be programmed via this register.
Once this register has been overwritten by software, the values
of the TCO fuses can be read using the Therm3 register.
Note:
For TCO operation, if TST [Direct DAC Test Enable] = 1, the
values in this field are sent directly to Bank B.
While this is a seven-bit field, the 7th bit is sign extended to 9
bits for TCO operation.
Hot Trip Point Setting (HTPS):
Sets the target value for the Hot trip point.
Lockable via TCO bit 7.
Catastrophic Trip Point Setting (CTPS):
Sets the target for the Catastrophic trip point. See also TST
[Direct DAC Connect Test Enable].
Lockable via TCO bit 7.
0/0/0/MCHBAR
CE2h
_0xxx__xxxx_h
R/WO; R/W/L
8 bits
R e g is te r F ie ld V a lu e
0 0 h to 3 F h
4 1 h to 7 fh
Description
Description
S ig n e d V a lu e
-3 F h to -1 h
0 0 h to 3 F h
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