QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 230

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

7.1.4
230
PCISTS1 - PCI Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register reports the occurrence of error conditions associated with primary side of
the “virtual” host-PCI Express bridge embedded within the (G)MCH.
10:9
Bit
Bit
15
14
13
12
11
1
0
Access
Access
R/WC
R/W
R/W
RO
RO
RO
RO
RO
Default
Default
Value
Value
00b
0b
0b
0b
0b
0b
0b
0b
Memory Access Enable (MAE):
ranges defined in the MBASE1, MLIMIT1, PMBASE1, and
PMLIMIT1 registers.
IO Access Enable (IOAE):
IOLIMIT1 registers.
Detected Parity Error (DPE):
Not Applicable or Implemented. Hardwired to 0. Parity
(generating poisoned TLPs) is not supported on the primary side
of this device (error forwarding is not supported).
Signaled System Error (SSE):
This bit is set when this Device sends an SERR due to detecting
an ERR_FATAL or ERR_NONFATAL condition and the SERR Enable
bit in the Command register is 1. Both received (if enabled by
BCTRL1[1]) and internally detected error messages do not affect
this field.
Received Master Abort Status (RMAS):
Not Applicable or Implemented. Hardwired to 0. The concept of a
master abort does not exist on primary side of this device.
Received Target Abort Status (RTAS):
Not Applicable or Implemented. Hardwired to 0. The concept of a
target abort does not exist on primary side of this device.
Signaled Target Abort Status (STAS):
Not Applicable or Implemented. Hardwired to 0. The concept of a
target abort does not exist on primary side of this device.
DEVSELB Timing (DEVT):
This device is not the subtractive decoded device on bus 0. This
bit field is therefore hardwired to 00 to indicate that the device
uses the fastest possible decode.
0: All of Device 1's memory space is disabled.
1: Enable the Memory and Pre-fetchable memory address
0: All of Device 1's I/O space is disabled.
1: Enable the I/O address range defined in the IOBASE1, and
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
0/1/0/PCI
06-07h
0010h
R/WC; RO
16 bits
(Sheet 3 of 3)
(Sheet 1 of 2)
Description
Description
Datasheet