QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 123

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

Device 0 Memory Mapped I/O Register
6.2.12
Datasheet
C0BNKARC - Channel 0 DRAM Bank Architecture
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register is used to program the bank architecture for each rank.
Channel
7:4
Bit
15:8
3
2
1
0
7:6
Bit
0
1
Access
R/W
R/W
R/W
R/W
Access
RO
R/W
Rank Clocks
RO
0 or 1
0 or 1
Default
Value
Default
0h
0b
0b
0b
0b
Value
00h
00b
SM_CK[1:0] / SM_CK#[1:0]
SM_CK[3:2] / SM_CK#[3:2]
Note: These signals are Not on the
Express Chipset.
Reserved
DIMM Clock Gate Enable Pair 3:
0: Tri-state the corresponding clock pair
1: Enable the corresponding clock pair
DIMM Clock Gate Enable Pair 2:
0: Tri-state the corresponding clock pair
1: Enable the corresponding clock pair
DIMM Clock Gate Enable Pair 1:
0: Tri-state the corresponding clock pair
1: Enable the corresponding clock pair
DIMM Clock Gate Enable Pair 0:
0: Tri-state the corresponding clock pair
1: Enable the corresponding clock pair
Reserved
Rank 3 Bank Architecture:
00: 4 Bank
01: 8 Bank
1X: Reserved
0/0/0/MCHBAR
10E-10Fh
0000h
R/W; RO
16 bits
Affected
Description
Description
Ultra Mobile 945GU
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