QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 358

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

10.3.2
10.3.2.1
358
The PCI Express host bridge is required to translate the memory-mapped PCI Express
configuration space accesses from the host processor to PCI Express configuration
cycles. To maintain compatibility with PCI configuration addressing mechanisms, it is
recommended that system software access the enhanced configuration space using 32-
bit operations (32-bit aligned) only.
See the current PCI Local Bus Specification for details of both the conventional PCI 2.3
compatible and PCI Express Enhanced configuration mechanisms and transaction rules.
Serial Digital Video Output (SDVO)
The SDVO description is located here because it is muxed onto the PCI Express x16
port pins. The AC/DC specifications are identical to the PCI Express Graphics interface.
SDVO electrical interface is based on the PCI Express interface, though the protocol
and timings are completely unique. Whereas PCI Express runs at a fixed frequency, the
frequency of the SDVO interface is dependant upon the active display resolution and
timing. The port can be dynamically configured in several modes to support display
configurations.
Essentially, an SDVO port will transmit display data in a high-speed, serial format
across differential AC coupled signals. An SDVO port consists of a sideband differential
clock pair and a number of differential data pairs.
SDVO Capabilities
SDVO ports can support a variety of display types including LVDS, DVI, TV-Out, and
external CE type devices. the Mobile Intel 945GM/GME/GMS/GU/GSE, 943/940GML and
Intel 945GT Express Chipsets utilize an external SDVO device to translate from SDVO
protocol and timings to the desired display format and timings. The Internal Graphics
controller can have one or two SDVO ports multiplexed on the x16 PCI Express
interface, in the case of the Mobile Intel 945GM/GME and Intel 945GT Express
Chipsets.
The SDVO port defines a two-wire point-to-point communication path between the
SDVO device and (G)MCH. The SDVO Control Clock and Data provide similar
functionality to I
(from the (G)MCH to the SDVO device) and will require the SDVO device to act as a
switch and direct traffic from the SDVO Control bus to the appropriate receiver.
Additionally, this Control bus will be able to run at faster speeds (up to 1 MHz) than a
traditional I
2
C interface would.
2
C. However unlike I
2
C, this interface is intended to be point-to-point
Functional Description
Datasheet