QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 52

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

2.7
Note:
52
Reset and Miscellaneous Signals
Some of the strappings mentioned in the table above do not exist on the Mobile Intel
945GMS/GSE Express Chipset. For more details, please refer to
strapping definitions.
RSTIN#
PWROK
H_BSEL [2:0]
(CFG[2:0])
CFG[17:3]
CFG[20:18]
PM_PM_BM_BUSY#
PM_EXTTS[1:0]#
ICH_SYNC#
Signal Name
HVCMOS
HVCMOS
HVCMOS
HVCMOS
HVCMOS
HVCMOS
AGTL+
AGTL+
Type
O
O
I
I
I
I
I
I
Reset In:
When asserted this signal will asynchronously reset the
(G)MCH logic. This signal is connected to the PLTRST# output
of the ICH7M.
This input has a Schmitt trigger to avoid spurious resets.
This input buffer is 3.3 V tolerant.
Power OK:
When asserted, PWROK is an indication to the (G)MCH that
core power has been stable for at least 99 ms and clocks stable
for at least 1 µs. Please see
This input buffer is 3.3-V tolerant.
Host Bus Speed Select:
At the deassertion of RSTIN#, the value sampled on these pins
determines the expected frequency of the bus.
External Pull-ups are required.
HW Straps:
CFG [17:3] has internal pull up.
HW Straps:
CFG [20:18] has internal pull down
(G)MCH Integrated Graphics Busy:
Used for PM synchronization with ICH. This signal should be
connected to PM_BM_BUSY# of the ICH-M.
External Thermal Sensor Input:
If the system temperature reaches a dangerously high value
then this signal can be used to trigger the start of system
memory throttling.
EXTTS1# can alternately be used to implement fast C4/C4E
exit. See
available on EXTTS0#.
ICH Synchronization:
Asserted to synchronize with ICH on faults. ICH_SYNC# must
be connected to ICH7M’s MCH_SYNC# signal.
Section 10.6.7
for details. This functionality is not
Description
Section 10.6.6
Chapter 12
for details.
Signal Description
for
Datasheet