QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 247

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

PCI Express Graphics Device 1 Configuration Registers (D1:F0)
7.1.27
7.1.28
Datasheet
MSI_CAPID - Message Signaled Interrupts Capability ID
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
When a device supports MSI it can generate an interrupt request to the processor by
writing a predefined data item (a message) to a predefined memory address.
The reporting of the existence of this capability can be disabled by setting MSICH
(CAPL[0] @ 7Fh). In that case walking this linked list will skip this capability and
instead go directly from the PCI PM capability to the PCI Express capability.
MC - Message Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
System software can modify bits in this register, but the device is prohibited from doing
so.
If the device writes the same message multiple times, only one of those messages is
guaranteed to be serviced. If all of them must be serviced, the device must not
generate the same message again until the driver services the earlier one.
15:8
15:8
7:0
Bit
Bit
7
Access
Access
RO
RO
RO
RO
Default
Default
Value
Value
A0h
05h
00h
0b
Pointer to Next Capability (PNC):
This contains a pointer to the next item in the capabilities list
which is the PCI Express* capability.
Capability ID (CID):
Value of 05h identifies this linked list item (capability structure)
as being for MSI registers.
Reserved
64-bit Address Capable (64AC):
Hardwired to 0 to indicate that the function does not implement
the upper 32 bits of the Message Address register and is
incapable of generating a 64-bit memory address.
This may need to change in future implementations when
addressable system memory exceeds the 32-b/4-GB limit.
0/1/0/PCI
90-91h
A005h
RO
16 bits
0/1/0/PCI
92-93h
0000h
R/W; RO
16 bits
Description
Description
247