QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 387

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

Functional Description
10.6.5.1
10.6.6
Figure 25.
Datasheet
CPU Sleep (HCPUSLP#) Signal Definition
The CPU’s sleep signal (SLP#) reduces power in the CPU by gating off unused clocks.
Unlike earlier configurations, this signal can be driven only by the (G)MCH’s HCPUSLP#
signal. Moving this ability to the (G)MCH allows dynamic use of the SLP# signal during
the CPU’s C2 state to reduce CPU power further while not performing snoops during C2.
Since the ICH is unaware of the snoop operations being done by the (G)MCH, the
HCPUSLP# signal was only asserted during the C3 states and below.
The (G)MCH host interface controller will ensure that no transactions will be initiated on
the FSB without having first met the required timing from the SLP# deassertion to the
assertion of BPRI#. This time is programmable from 0 to 31 clocks (8-clock default).
(G)MCH will control HCPUSLP# and enforce the configured timing rules associated with
this. This allows the (G)MCH to enforce the timing of the SLP# deassertion to BPRI#
assertion during C3 to C2 or C3 to C0 transitions.
PWROK Timing Requirements for Power-up,
Resume from S3-Cold and S3-Hot
The diagrams below highlight the timing requirements for the (G)MCH PWROK signal
for Power-up, resume from S3-Cold and S3-Hot:
Upon Power-up and Resume from S3-Cold
NOTE:
1.
2.
3.
Timings t1, t2 apply for both Power-up and Resume from S3-Cold events.
t1: All (G)MCH power supplies should be valid at least 99ms before PWROK assertion.
t2: (G)MCH clocks should be running and stable at least 1us before PWROK assertion.
GMCH PWROK
GMCH PWROK
GMCH PWROK
GMCH PWROK
GMCH
GMCH
GMCH
GMCH
HCLK/GCLK
HCLK/GCLK
HCLK/GCLK
HCLK/GCLK
PLL
PLL
PLL
PLL
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
t0>0
t0>0
t1>=99ms
t1>=99ms
t2>=1us
t2>=1us
Running & Stable
Running & Stable
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