C8051F226DK Silicon Laboratories Inc, C8051F226DK Datasheet - Page 104

• Manufacturer Part Number: C8051F226DK
• Description: DEV KIT F220/221/226/230/231/236
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F226DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F22x and C8051F23x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F226
• Silicon Family Name: C8051F2xx
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F220, 221, 226, 230, 231, 236
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1241

C8051F2xx
104
Bit7:
Bit6:
Bits 5–2: UNUSED. Read = 0000b, Write = don't care.
Bit1:
Bit0:
Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bit 3:
Bits 2–1: UNUSED. Read = 00b, Write = don't care.
Bit 0:
GWPUD P3WPUD P2WPUD P1WPUD P0WPUD
R/W
Bit7
Bit7
R
-
UNUSED. Read = 0.
SYSCKE: SYSCLK Output Enable Bit
0: SYSCLK unavailable at the port pin.
1: SYSCLK output routed to pin P1.6
CP1OEN: Comparator 1 Output Enable bit.
0: CP1 unavailable at Port pin.
1: CP1 routed to Port Pin P1.5.
CP0OEN: Comparator 0 Output Enable Bit
0: CP0 unavailable at port pin.
1: CP0 routed to port pin P1.2.
GWPUD: Global Port I/O Weak Pull-up Disable Bit
0: Weak Pull-ups Enabled for all ports.
1: Weak Pull-ups Disabled (Bits 6–3 Don't cares)
P3WPUD: Port 3 Weak Pull-up Disable Bit
0: Weak Pull-ups Enabled for port 3
1: Weak Pull-ups Disabled for port 3
P2WPUD: Port 2 Weak Pull-up Disable Bit
0: Weak Pull-ups Enabled for port 2.
1: Weak Pull-ups Disabled for port 2
P1WPUD: Port 1 Weak Pull-up Disable Bit
0: Weak Pull-ups Enabled for port 1
1: Weak Pull-ups Disabled for port 1
P0WPUD: Port 0 Weak Pull-up Disable Bit
0: Weak Pull-ups Enabled for port 0
1: Weak Pull-ups Disabled for port 0
SPI0OEN: SPI Bus I/O Enable Bit.
0: SPI I/O unavailable at port pins.
1: SCK, MISO, MOSI, NSS routed to pins P2.0, P2.1, P2.2, and P2.3 respectively.
SYSCKE
R/W
R/W
Bit6
Bit6
SFR Definition 14.2. PRT1MX: Port I/O MUX Register 1
SFR Definition 14.3. PRT2MX: Port I/O MUX Register 2
R/W
Bit5
Bit5
R
-
R/W
Bit4
Bit4
R
-
Rev. 1.6
R/W
Bit3
Bit3
R
-
R/W
Bit2
Bit2
R
-
-
CP1OEN CP0OEN
R/W
R/W
Bit1
Bit1
-
SPI0OEN
R/W
R/W
Bit0
Bit0
SFR Address:
SFR Address:
Reset Value
Reset Value
00000000
00000000
0xE3
0xE2