C8051F226DK Silicon Laboratories Inc, C8051F226DK Datasheet - Page 121

• Manufacturer Part Number: C8051F226DK
• Description: DEV KIT F220/221/226/230/231/236
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F226DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F22x and C8051F23x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F226
• Silicon Family Name: C8051F2xx
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F220, 221, 226, 230, 231, 236
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1241

C8051F2xx
16.1.3. Mode 2: 9-Bit UART, Fixed Baud Rate
Mode 2 provides asynchronous, full-duplex communication using a total of eleven bits per data byte: a start
bit, 8 data bits (LSB first), a programmable ninth data bit, and a stop bit (see timing diagram in
Figure 16.6). On transmit, the ninth data bit is determined by the value in TB8 (SCON.3). It can be
assigned the value of the parity flag P in the PSW or used in multiprocessor communications. On receive,
the ninth data bit goes into RB8 (SCON.2) and the stop bit is ignored.
Data transmission begins when an instruction writes a data byte to the SBUF register. The TI Transmit
Interrupt Flag (SCON.1) is set at the end of the transmission (the beginning of the stop-bit time). Data
reception can begin any time after the REN Receive Enable bit (SCON.4) is set to logic 1. After the stop bit
is received, the data byte will be loaded into the SBUF receive register if the following conditions are met:
RI must be logic 0, and if SM2 is logic 1, the 9th bit must be logic 1.
If these conditions are met, the eight bits of data is stored in SBUF, the ninth bit is stored in RB8 and the RI
flag is set. If these conditions are not met, SBUF and RB8 will not be loaded and the RI flag will not be set.
An interrupt will occur if enabled when either TI or RI are set.
The baud rate in Mode 2 is a direct function of the system clock frequency as follows:
Mode 2 Baud Rate = 2SMOD x (SYSCLK / 64).
The SMOD bit (PCON.7) selects whether to divide SYSCLK by 32 or 64. In the formula, 2 is raised to the
power SMOD, resulting in a baud rate of either 1/32 or 1/64 of the system clock frequency. On reset, the
SMOD bit is logic 0, thus selecting the lower speed baud rate by default.
MARK
START
STOP
D0
D1
D2
D3
D4
D5
D6
D7
D8
BIT
BIT
SPACE
BIT TIMES
BIT SAMPLING
Figure 16.6. UART Modes 2 and 3 Timing Diagram
16.1.4. Mode 3: 9-Bit UART, Variable Baud Rate
Mode 3 is the same as Mode 2 in all respects except the baud rate is variable. The baud rate is deter-
mined in the same manner as for Mode 1. Mode 3 operation transmits 11 bits: a start bit, 8 data bits (LSB
first), a programmable ninth data bit, and a stop bit. Timer 1 or Timer 2 overflows generate the baud rate
just as with Mode 1. In summary, Mode 3 transmits using the same protocol as Mode 2 but with Mode 1
baud rate generation.
Rev. 1.6
121