C8051F226DK Silicon Laboratories Inc, C8051F226DK Datasheet - Page 93

• Manufacturer Part Number: C8051F226DK
• Description: DEV KIT F220/221/226/230/231/236
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F226DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F22x and C8051F23x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F226
• Silicon Family Name: C8051F2xx
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F220, 221, 226, 230, 231, 236
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1241

C8051F2xx
12.4. External Reset
The external RST pin provides a means for external circuitry to force the CIP-51 into a reset state. Assert-
ing an active-low signal on the RST pin will cause the CIP-51 to enter the reset state. Although there is a
weak pull-up, it may be desirable to provide an external pull-up and/or decoupling of the RST pin to avoid
erroneous noise-induced resets. The CIP-51 will remain in reset until at least 12 clock cycles after the
active-low RST signal is removed. The PINRSF flag (RSTSRC.0) is set on exit from an external reset.
The RST pin is 5 V tolerant.
12.5. Missing Clock Detector Reset
The Missing Clock Detector is essentially a one-shot circuit that is triggered by the MCU system clock. If
the system clock goes away for more than 100msec, the one-shot will time out and generate a reset. After
a Missing Clock Detector reset, the MCDRSF flag (RSTSRC.2) will be set, signifying the MSD as the reset
source; otherwise, this bit reads 0. The state of the RST pin is unaffected by this reset. Setting the
MSCLKE bit in the OSCICN register (see SFR Definition 13.1) enables the Missing Clock Detector.
12.6. Comparator 0 Reset
Comparator 0 can be configured as a reset input by writing a 1 to the C0RSEF flag (RSTSRC.5). Compar-
ator 0 should be enabled using CPT0CN.7 (see SFR Definition 8.1) prior to writing to C0RSEF to prevent
any turn-on chatter on the output from generating an unwanted reset. When configured as a reset, if the
non-inverting input voltage (on CP0+) is less than the inverting input voltage (on CP0–), the MCU is put
into the reset state. After a Comparator 0 Reset, the C0RSEF flag (RSTSRC.5) will read 1 signifying Com-
parator 0 as the reset source; otherwise, this bit reads 0. The state of the RST pin is unaffected by this
reset.
12.7. Watchdog Timer Reset
The MCU includes a programmable Watchdog Timer (WDT) running off the system clock. The WDT will
force the MCU into the reset state when the watchdog timer overflows. To prevent the reset, the WDT
must be restarted by application software before the overflow occurs. If the system experiences a soft-
ware/hardware malfunction preventing the software from restarting the WDT, the WDT will overflow and
cause a reset. This should prevent the system from running out of control.
The WDT is automatically enabled and started with the default maximum time interval on exit from all
resets. If desired, the WDT can be disabled by system software or locked 'on' to prevent accidental dis-
abling. Once locked, the WDT cannot be disabled until the next system reset. The state of the RST pin is
unaffected by this reset.
12.7.1. Watchdog Usage
The WDT consists of a 21-bit timer running from the programmed system clock. The timer measures the
period between specific writes to its control register. If this period exceeds the programmed limit, a WDT
reset is generated. The WDT can be enabled and disabled as needed in software, or can be permanently
enabled if desired. Watchdog features are controlled via the Watchdog Timer Control Register (WDTCN)
shown in SFR Definition 12.1.
Enable/Reset WDT
The watchdog timer is both enabled and reset by writing 0xA5 to the WDTCN register. The user's applica-
tion software should include periodic writes of 0xA5 to WDTCN as needed to prevent a watchdog timer
overflow. The WDT is enabled and reset as a result of any system reset.
Rev. 1.6
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