C8051F226DK Silicon Laboratories Inc, C8051F226DK Datasheet - Page 89
C8051F226DK
Manufacturer Part Number
C8051F226DK
Description
DEV KIT F220/221/226/230/231/236
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet
1.C8051F226DK.pdf
(146 pages)
Specifications of C8051F226DK
Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F22x and C8051F23x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F226
Silicon Family Name
C8051F2xx
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F220, 221, 226, 230, 231, 236
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1241
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Bit7:
Bit6:
Bits5–4: UNUSED. Read = 00b, Write = don't care.
Bits3–0: FLASCL: Flash Memory Timing Prescaler.
Bits 7–0: FLACL: Flash Memory Access Limit.
FOSE
R/W
R/W
Bit7
Bit7
FOSE: Flash One-Shot Timer Enable
0: Flash One-shot timer disabled.
1: Flash One-shot timer enabled
FRAE: Flash Read Always Enable
0: Flash reads per one-shot timer
1: Flash always in read mode
This register specifies the prescaler value for a given system clock required to generate the
correct timing for Flash write/erase operations. If the prescaler is set to 1111b, Flash
write/erase operations are disabled.
0000: System Clock < 50 kHz
0001: 50 kHz < System Clock < 100 kHz
0010: 100 kHz < System Clock < 200 kHz
0011: 200 kHz < System Clock < 400 kHz
0100: 400 kHz < System Clock < 800 kHz
0101: 800 kHz < System Clock < 1.6 MHz
0110: 1.6 MHz < System Clock < 3.2 MHz
0111: 3.2 MHz < System Clock < 6.4 MHz
1000: 6.4 MHz < System Clock < 12.8 MHz
1001: 12.8 MHz < System Clock < 25.6 MHz
1010: 25.6 MHz < System Clock < 51.2 MHz*
1011, 1100, 1101, 1110: Reserved Values
1111: Flash Memory Write/Erase Disabled
The prescaler value is the smallest value satisfying the following equation:
FLASCL > log2(System Clock / 50kHz)
*For test purposes. The C8051F2xx is not guaranteed to operate over 25 MHz.
This register holds the high byte of the 16-bit program memory read/write/erase limit
address. The entire 16-bit access limit address value is calculated as 0xNN00 where NN is
replaced by contents of FLACL. A write to this register sets the Flash Access Limit. Any
subsequent writes are ignored until the next reset.
SFR Definition 10.2. FLSCL: Flash Memory Timing Prescaler
FRAE
R/W
R/W
Bit6
Bit6
SFR Definition 10.3. FLACL: Flash Access Limit
R/W
Bit5
R/W
Bit5
-
R/W
Bit4
R/W
Bit4
-
Rev. 1.6
R/W
Bit3
R/W
Bit3
R/W
Bit2
R/W
Bit2
FLASCL
R/W
Bit1
R/W
Bit1
C8051F2xx
R/W
Bit0
R/W
Bit0
SFR Address:
Reset Value
SFR Address:
00000000
Reset Value
10001111
0xB7
0xB6
89
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