C8051F226DK Silicon Laboratories Inc, C8051F226DK Datasheet - Page 110

• Manufacturer Part Number: C8051F226DK
• Description: DEV KIT F220/221/226/230/231/236
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F226DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F22x and C8051F23x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F226
• Silicon Family Name: C8051F2xx
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F220, 221, 226, 230, 231, 236
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1241

C8051F2xx
15. Serial Peripheral Interface Bus
The Serial Peripheral Interface (SPI) provides access to a four-wire, full-duplex, serial bus. SPI supports
the connection of multiple slave devices to a master device on the same bus. A separate slave-select sig-
nal (NSS) is used to select a slave device and enable a data transfer between the master and the selected
slave. Multiple masters on the same bus are also supported. Collision detection is provided when two or
more masters attempt a data transfer at the same time. The SPI can operate as either a master or a slave.
When the SPI is configured as a master, the maximum data transfer rate (bits/sec) is one-half the system
clock frequency.
When the SPI is configured as a slave, the maximum data transfer rate (bits/sec) for full-duplex operation
is 1/10 the system clock frequency, provided that the master issues SCK, NSS, and the serial input data
synchronously with the system clock. If the master issues SCK, NSS, and the serial input data asynchro-
nously, the maximum data transfer rate (bits/sec) must be less that 1/10 the system clock frequency. In the
special case where the master only wants to transmit data to the slave and does not need to receive data
from the slave (i.e. half-duplex operation), the SPI slave can receive data at a maximum data transfer rate
(bits/sec) of ¼ the system clock frequency. This is provided that the master issues SCK, NSS, and the
serial input data synchronously with the system clock.
110
SYSCLK
S
C
R
7
S
C
R
6
Clock Divide
SPI0CKR
S
C
R
5
SFR Bus
SPI0DAT
Logic
Write to
C
R
S
4
S
C
R
3
Data Path
Control
S
C
R
2
Receive Data Register
C
R
7
S
1
S
C
R
6
0
Shift Register
5
SPI CONTROL LOGIC
4
Figure 15.1. SPI Block Diagram
C
K
P
H
A
3
O
C
K
P
L
2
(Master Mode)
SFR Bus
SPI0CFG
SPI Clock
C
1
B
2
SPI0DAT
SPI0DAT
Read
Bit Count
B
C
0
1
Logic
B
C
0
R
F
S
2
Tx Data
R
S
F
1
Rx Data
F
R
S
0
Rev. 1.6
Pin Control
S
P
F
Control
I
Interface
Logic
Pin
W
O
C
L
M
O
D
F
SPI0CN
R
X
O
V
R
N
T
X
B
S
Y
MISO
MOSI
SCK
NSS
S
V
S
E
L
L
M
S
T
E
N
S
P
E
N
I
O
R
M
U
P
T
2
X
SPI IRQ
P2.0 SCK
P2.1 MISO
P2.2 MOSI
P2.3 NSS