C8051F226DK Silicon Laboratories Inc, C8051F226DK Datasheet - Page 117

• Manufacturer Part Number: C8051F226DK
• Description: DEV KIT F220/221/226/230/231/236
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F226DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F22x and C8051F23x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F226
• Silicon Family Name: C8051F2xx
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F220, 221, 226, 230, 231, 236
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1241

16. UART
Description
The CIP-51 includes a serial port (UART) capable of asynchronous transmission. The UART can function
in full duplex mode. In all modes, receive data is buffered in a holding register. This allows the UART to
start reception of a second incoming data byte before software has finished reading the previous data byte.
The UART has an associated Serial Control Register (SCON) and a Serial Data Buffer (SBUF) in the
SFRs. The single SBUF location provides access to both transmit and receive registers. Reads access
the Receive register and writes access the Transmit register automatically.
The UART is capable of generating interrupts if enabled. The UART has two sources of interrupts: a
Transmit Interrupt flag, TI (SCON.1) set when transmission of a data byte is complete, and a Receive Inter-
rupt flag, RI (SCON.0) set when reception of a data byte is complete. The UART interrupt flags are not
cleared by hardware when the CPU vectors to the interrupt service routine. They must be cleared manu-
ally by software. This allows software to determine the cause of the UART interrupt (transmit complete or
receive complete).
S
M
O
D
Overflow
Overflow
Timer 1
Timer 2
PCON
SYSCLK
2
M
S
0
Baud Rate Generation Logic
SMOD
1
0
S
M
1
M
S
2
SCON
R
E
N
32
64
12
T
B
8
R
B
8
T
I
SMOD
TCLK
RCLK
R
I
0
1
0
1
1
0
16
16
R
C
K
L
T2CON
Figure 16.1. UART Block Diagram
T
C
L
K
SFR Bus
00
01
10
11
00
01
10
11
SM0, SM1
{MODE}
Write to
SBUF
Rev. 1.6
Tx Clock
Rx Clock
Start
Start
Bit Detector
Interrupt
Serial
Port
D
TB8
SET
CLR
Stop Bit
Q
Gen.
SBUF
Read
TI
RI
Tx Control
Tx IRQ
Rx IRQ
Rx Control
Zero Detector
SFR Bus
Input Shift Register
SBUF
SBUF
Enable
REN
Shift
(9 bits)
0x1FF
MSB
RB8
Load SBUF
SBUF
Data
Send
Load
Shift
Shift
RX
TX
C8051F2xx
Port0 MUX
Port0 MUX
P0.0
P0.1
Port I/O
117