C8051F226DK Silicon Laboratories Inc, C8051F226DK Datasheet - Page 92

• Manufacturer Part Number: C8051F226DK
• Description: DEV KIT F220/221/226/230/231/236
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F226DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F22x and C8051F23x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F226
• Silicon Family Name: C8051F2xx
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F220, 221, 226, 230, 231, 236
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1241

C8051F2xx
12.1. Power-on Reset
The CIP-51 incorporates a power supply monitor that holds the MCU in the reset state until V
above the VRST level during power-up. (See Figure 12.2 for timing diagram, and refer to Table 12.1 for
the Electrical Characteristics of the power supply monitor circuit.) The RST pin is asserted (low) until the
end of the 100msec V
packages, the V
MONEN pin low. The MONEN pin should never be left floating. On 32-pin packages, the V
always enabled and cannot be disabled.
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. All of the other
reset flags in the RSTSRC Register are indeterminate. PORSF is cleared by all other resets. Since all
resets cause program execution to begin at the same location (0x0000), software can read the PORSF
flag to determine if a power-up was the cause of reset. The content of internal data memory should be
assumed to be undefined after a power-on reset.
12.2. Software Forced Reset
Writing a 1 to the PORSF bit forces a Power-On Reset as described in Section 12.1.
12.3. Power-fail Reset
When the V
and power-down transition or power irregularity causes V
will drive the RST pin low and return the CIP-51 to the reset state (see Figure 12.2). When V
a level above VRST, the CIP-51 will leave the reset state in the same manner as that for the power-on
reset. Note that even though internal data memory contents are not altered by the power-fail reset, it is
impossible to determine if V
set, the data may no longer be valid.
92
Logic HIGH
Logic LOW
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2.70
2.55
2.0
1.0
monitor is enabled, the MONEN pin (not on C8051F221/F231 32 pin parts) is "pulled high",
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monitor is enabled by pulling the MONEN pin high and is disabled by pulling the
/RST
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Monitor timeout in order to allow the V
Figure 12.2. V
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V
RST
dropped below the level required for data retention. If the PORSF flag is
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100ms
Monitor Timing Diagram
Rev. 1.6
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to drop below VRST, the power supply monitor
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supply to become stable. On 48-pin
100ms
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DD
monitor is
returns to
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t
rises