C8051F226DK Silicon Laboratories Inc, C8051F226DK Datasheet - Page 142

• Manufacturer Part Number: C8051F226DK
• Description: DEV KIT F220/221/226/230/231/236
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F226DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F22x and C8051F23x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F226
• Silicon Family Name: C8051F2xx
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F220, 221, 226, 230, 231, 236
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1241

C8051F2xx
142
DATA7 DATA6
This register is used to read or write data to the Flash memory across the JTAG interface.
Bits9–2: DATA7–0: Flash Data Byte.
Bit1:
Bit0:
This register controls the Flash read timing circuit and the prescaler required to generate the correct
timing for Flash operations.
Bit7:
Bit6:
Bits5–4: UNUSED. Read = 00b, Write = don't care.
Bits3–0: FLSCL3–0: Flash Prescaler Control Bits.
FOSE
Bit9
Bit7
FAIL: Flash Fail Bit.
0:
1:
BUSY: Flash Busy Bit.
0:
1:
FOSE: Flash One-Shot Enable Bit.
0: Flash read strobe is a full clock-cycle wide.
1: Flash read strobe is 50nsec.
FRAE: Flash Read Always Bit.
0: The Flash output enable and sense amplifier enable are on only when needed to read the
1: The Flash output enable and sense amplifier enable are always on. This can be used to
The FLSCL3–0 bits control the prescaler used to generate timing signals for Flash opera-
tions. Its value should be written before any Flash write or erase operations are initiated.
The value written should be the smallest integer for which: 

FLSCL[3:0] > log2(fSYSCLK / 50kHz)

Where fSYSCLK is the system clock frequency. All Flash read/write/erase operations are
disallowed when FLSCL[3:0] = 1111b.
Bit8
JTAG Register Definition 18.5. FLASHSCL: JTAG Flash Scale
JTAG Register Definition 18.4. FLASHDAT: JTAG Flash Data
FRAE
Flash memory.
limit the variations in digital supply current due to switching the sense amplifiers, thereby
reducing digitally induced noise.
Bit6
DATA5
Previous Flash memory operation was successful.
Previous Flash memory operation failed. Usually indicates the associated memory
location was locked.
Flash interface logic is not busy.
not initiate another operation
Flash interface logic is processing a request. Reads or writes while BUSY = 1 will
Bit7
Bit5
-
DATA4 DATA3 DATA2 DATA1
Bit6
Bit4
-
Bit5
FLSCL3
Rev. 1.6
Bit4

Bit3
Bit3
FLSCL2
Bit2
DATA0
Bit2
FLSCL1
Bit1
FAIL
Bit1
FLSCL0
BUSY
Bit0
Bit0
0000000000
Reset Value
Reset Value
00000000