C8051F226DK Silicon Laboratories Inc, C8051F226DK Datasheet - Page 72

• Manufacturer Part Number: C8051F226DK
• Description: DEV KIT F220/221/226/230/231/236
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F226DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F22x and C8051F23x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F226
• Silicon Family Name: C8051F2xx
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F220, 221, 226, 230, 231, 236
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1241

C8051F2xx
72
Bit7:
Bit6:
Bit5:
Bits4–3: RS1–RS0: Register Bank Select. 
Bit2:
Bit1:
Bit0:
R/W
CY
Bit7
RS1
CY: Carry Flag. 
This bit is set when the last arithmetic operation results in a carry (addition) or a borrow
(subtraction). It is cleared to 0 by all other arithmetic operations.
AC: Auxiliary Carry Flag. 
This bit is set when the last arithmetic operation results in a carry into (addition) or a borrow
from (subtraction) the high order nibble. It is cleared to 0 by all other arithmetic operations.
F0: User Flag 0. 
This is a bit-addressable, general-purpose flag for use under software control.
These bits select which register bank is used during register accesses. 
Note: Any instruction which changes the RS1–RS0 bits must not be immediately followed by
the “MOV Rn, A” instruction.
OV: Overflow Flag. 
This bit is set to 1 under the following circumstances:
•An ADD, ADDC, or SUBB instruction causes a sign-change overflow.
•A MUL instruction results in an overflow (result is greater than 255).
•A DIV instruction causes a divide-by-zero condition.
The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all other
cases.
F1: User Flag 1. 
This is a bit-addressable, general purpose flag for use under software control.
PARITY: Parity Flag. 
This bit is set to 1 if the sum of the eight bits in the accumulator is odd and cleared if the sum
is even.
0
0
1
1
R/W
AC
Bit6
RS0
0
1
0
1
SFR Definition 9.4. PSW: Program Status Word
R/W
Bit5
F0
Register Bank
0
1
2
3
RS1
R/W
Bit4
0x08–0x0F
0x18–0x1F
0x00–0x07
0x10–0x17
Rev. 1.6
Address
RS0
R/W
Bit3
R/W
OV
Bit2
R/W
Bit1
F1
addressable)
PARITY
Bit0
(bit
R
SFR Address:
Reset Value
00000000
0xD0