C8051F226DK Silicon Laboratories Inc, C8051F226DK Datasheet - Page 124

• Manufacturer Part Number: C8051F226DK
• Description: DEV KIT F220/221/226/230/231/236
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F226DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F22x and C8051F23x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F226
• Silicon Family Name: C8051F2xx
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F220, 221, 226, 230, 231, 236
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1241

C8051F2xx
124
Bits7–6: SM0–SM1: Serial Port Operation Mode. 
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
SM0
R/W
Bit7
SM0
These bits select the Serial Port Operation Mode.
0
0
1
1
SM2: Multiprocessor Communication Enable. 
The function of this bit is dependent on the Serial Port Operation Mode.
Mode 0: No effect 
Mode 1: Checks for valid stop bit.
Mode 2 and 3: Multiprocessor Communications Enable.
REN: Receive Enable. 
This bit enables/disables the UART receiver.
0: UART reception disabled.
1: UART reception enabled.
TB8: Ninth Transmission Bit.
The logic level of this bit will be assigned to the ninth transmission bit in Modes 2 and 3. It is
not used in Modes 0 and 1. Set or cleared by software as required.
RB8: Ninth Receive Bit. 
The bit is assigned the logic level of the ninth bit received in Modes 2 and 3. In Mode 1, if
SM2 is logic 0, RB8 is assigned the logic level of the received stop bit. RB8 is not used in
Mode 0.
TI: Transmit Interrupt Flag. 
Set by hardware when a byte of data has been transmitted by the UART (after the 8
Mode 0, or at the beginning of the stop bit in other modes). When the UART interrupt is
enabled, setting this bit causes the CPU to vector to the UART interrupt service routine.
This bit must be cleared manually by software
RI: Receive Interrupt Flag. 
Mode 0, or after the stop bit in other modes – see SM2 bit for exception). When the UART
interrupt is enabled, setting this bit causes the CPU to vector to the UART interrupt service
routine. This bit must be cleared manually by software.
Set by hardware when a byte of data has been received by the UART (after the 8
SM1
R/W
Bit6
0: Logic level of stop bit is ignored.
1: RI will only be activated if stop bit is logic level 1.
0: Logic level of ninth bit is ignored.
1: RI is set and an interrupt is generated only when the ninth bit is logic 1.
SM1
0
1
0
1
SFR Definition 16.2. SCON: Serial Port Control
SM2
R/W
Bit5
Mode 0: Synchronous Mode
Mode 1: 8-Bit UART, Variable Baud Rate
Mode 2: 9-Bit UART, Fixed Baud Rate
Mode 3: 9-Bit UART, Variable Baud Rate
REN
R/W
Bit4
TB8
Mode
R/W
Bit3
Rev. 1.6
RB8
R/W
Bit2
R/W
Bit1
TI
(bit addressable)
R/W
Bit0
RI
SFR Address:
Reset Value
th
00000000
th
0x98
bit in
bit in