C8051F226DK Silicon Laboratories Inc, C8051F226DK Datasheet - Page 64
C8051F226DK
Manufacturer Part Number
C8051F226DK
Description
DEV KIT F220/221/226/230/231/236
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet
1.C8051F226DK.pdf
(146 pages)
Specifications of C8051F226DK
Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F22x and C8051F23x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F226
Silicon Family Name
C8051F2xx
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F220, 221, 226, 230, 231, 236
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1241
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C8051F2xx
64
Rn - Register R0–R7 of the currently selected register bank.
@Ri - Data RAM location addressed indirectly through register R0–R1
rel - 8-bit, signed (two’s compliment) offset relative to the first byte of the following instruction. Used by
SJMP and all conditional jumps.
direct - 8-bit internal data location’s address. This could be a direct-access Data RAM location (0x00–
0x7F) or an SFR (0x80–0xFF).
#data - 8-bit constant
#data 16 - 16-bit constant
bit - Direct-addressed bit in Data RAM or SFR.
addr 11 - 11-bit destination address used by ACALL and AJMP. The destination must be within the
same 2 kB page of program memory as the first byte of the following instruction.
addr 16 - 16-bit destination address used by LCALL and LJMP. The destination may be anywhere
within the 8 kB program memory space.
There is one unused opcode (0xA5) that performs the same function as NOP.
All mnemonics copyrighted © Intel Corporation 1980.
Notes on Registers, Operands and Addressing Modes:
Rev. 1.6
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