C8051F226DK Silicon Laboratories Inc, C8051F226DK Datasheet - Page 118

DEV KIT F220/221/226/230/231/236

C8051F226DK

Manufacturer Part Number
C8051F226DK
Description
DEV KIT F220/221/226/230/231/236
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet

Specifications of C8051F226DK

Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F22x and C8051F23x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F226
Silicon Family Name
C8051F2xx
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F220, 221, 226, 230, 231, 236
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1241
C8051F2xx
16.1. UART Operational Modes
The UART provides four operating modes (one synchronous and three asynchronous) selected by setting
configuration bits in the SCON register. These four modes offer different baud rates and communication
protocols. The four modes are summarized in Table 16.1 below. Detailed descriptions follow.
16.1.1. Mode 0: Synchronous Mode
Mode 0 provides synchronous, half-duplex communication. Serial data is transmitted and received on the
RX pin. The TX pin provides the shift clock for both transmit and receive. The MCU must be the master
since it generates the shift clock for transmission in both directions (see the interconnect diagram in
Figure 16.2).
Eight data bits are transmitted/received, LSB first (see the timing diagram in Figure 16.3). Data transmis-
sion begins when an instruction writes a data byte to the SBUF register. The TI Transmit Interrupt Flag
(SCON.1) is set at the end of the eighth bit time. Data reception begins when the REN Receive Enable bit
(SCON.4) is set to logic 1 and the RI Receive Interrupt Flag (SCON.0) is cleared. One cycle after the
eighth bit is shifted in, the RI flag is set and reception stops until software clears the RI bit. An interrupt will
occur if enabled when either TI or RI are set.
The Mode 0 baud rate is system clock frequency divided by twelve.
118
Mode
0
1
2
3
Synchronization
Asynchronous
Asynchronous
Asynchronous
Synchronous
RX (data out)
RX (data in)
TX (clk out)
TX (clk out)
Figure 16.3. UART Mode 0 Timing Diagram
Figure 16.2. UART Mode 0 Interconnect
C8051Fxxx
Table 16.1. UART Modes
D0
D0
Timer 1 or Timer 2 Overflow
Timer 1 or Timer 2 Overflow
SYSCLK/32 or SYSCLK/64
D1
TX
RX
D1
Baud Clock
MODE 0 TRANSMIT
SYSCLK/12
MODE 0 RECEIVE
Rev. 1.6
D2
D2
D3
D3
CLK
DATA
D4
8 Extra Outputs
D4
D5
Reg.
Shift
D5
Data Bits
D6
D6
8
8
9
9
D7
D7
Start/Stop Bits
1 Start, 1 Stop
1 Start, 1 Stop
1 Start, 1 Stop
None

Related parts for C8051F226DK