C8051F226DK Silicon Laboratories Inc, C8051F226DK Datasheet - Page 58

• Manufacturer Part Number: C8051F226DK
• Description: DEV KIT F220/221/226/230/231/236
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F226DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F22x and C8051F23x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F226
• Silicon Family Name: C8051F2xx
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F220, 221, 226, 230, 231, 236
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1241

C8051F2xx
9.
General Description
The MCU’s system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the
MCS-51
ware. The MCU has a superset of all the peripherals included with a standard 8051. Included are three
16-bit counter/timers (see description in Section 17), a full-duplex UART (see description in Section 16),
256 bytes of internal RAM, 128 byte Special Function Register (SFR) address space (see Section 9.3),
and four byte-wide I/O Ports (see description in Section 14). The CIP-51 also includes on-chip debug
hardware (see description in Section 18), and interfaces directly with the MCU’s analog and digital subsys-
tems providing a complete data acquisition or control-system solution in a single integrated circuit.
Features
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as
additional custom peripherals and functions to extend its capability (see Figure 9.1 for a block diagram).
The CIP-51 includes the following features:
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Fully Compatible with MCS-51 Instruction Set
25 MIPS Peak Throughput with 25 MHz Clock
0 to 25 MHz Clock Frequency
256 Bytes of Internal RAM
Optional 1024 Bytes of XRAM
8 kB Flash Program Memory
CIP-51 Microcontroller
TM
instruction set. Standard 803x/805x assemblers and compilers can be used to develop soft-
RESET
CLOCK
STOP
IDLE
ACCUMULATOR
Figure 9.1. CIP-51 Block Diagram
PROGRAM COUNTER (PC)
CONTROL
PSW
PRGM. ADDRESS REG.
LOGIC
POWER CONTROL
PC INCREMENTER
DATA POINTER
REGISTER
BUFFER
TMP1
PIPELINE
ALU
TMP2
Rev. 1.6
DATA BUS
DATA BUS
D8
D8
D8
•
•
•
•
•
•
A16
D8
D8
D8
D8
B REGISTER
Four Byte-Wide I/O Ports
Extended Interrupt Handler
Reset Input
Power Management Modes
On-chip Debug Circuitry
Program and Data Memory Security
REGISTER
ADDRESS
INTERFACE
INTERFACE
INTERRUPT
INTERFACE
MEMORY
SRAM
SFR
BUS
MEM_WRITE_DATA
SFR_WRITE_DATA
MEM_READ_DATA
STACK POINTER
(256 X 8)
SFR_READ_DATA
SRAM
MEM_CONTROL
EMULATION_IRQ
MEM_ADDRESS
SFR_CONTROL
SFR_ADDRESS
SYSTEM_IRQs